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AR# 53747

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 - Incorrect RXCDR_CFG attributes in GTH results in non-working link


Version Found: v1.4
Silicon Revision: GES only
Version Resolved and other Known Issues: See (Xilinx Answer 47441).

When targeting a GES silicon with PCI Express Gen3 v1.4 core at Gen3 speed, it has been found that the link will not work due to incorrect RXCDR_CFG settings in GTH. This issue was NOT seen in production silicon with PCI Express Gen3 v1.3 core

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


For GES silicon only, please apply the following work-around:

Find the <core_name>_pipe_drp.v file, replace the following code:

    localparam          GEN3_RXCDR_CFG_A_GTH_S    = 16'h0018;              // 16'h0018 Sync
    localparam          GEN3_RXCDR_CFG_A_GTH_A    = 16'h8018;              // 16'h8018 Async


    localparam          GEN3_RXCDR_CFG_A_GTH_S    = 16'h001A;              // 16'h001A Sync
    localparam          GEN3_RXCDR_CFG_A_GTH_A    = 16'h801A;              // 16'h801A Async

Details of valid GES GTH transceiver settings can be found in (Xilinx Answer 51625).

For Production silicon, please use at least PCI Express GEN3 core v1.3 available in 2013.1 tool release.

Revision History
01/10/2013 - Initial release
03/19/2013 - Updated work-around section with new fix
03/03/2013 - Added silicon revision affected by this issue.

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AR# 53747
Date Created 01/10/2013
Last Updated 08/26/2013
Status Active
Type Known Issues
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)