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AR# 53776: Generating Quick Test Cases for Xilinx Integrated PCI Express Block and Serial RapidIO Cores Verilog Simulation
Generating Quick Test Cases for Xilinx Integrated PCI Express Block and Serial RapidIO Cores Verilog Simulation
This Answer Record provides techniques for generating quick test cases for Xilinx Integrated PCI Express Block and Serial RapidIO Cores Verilog simulation in a downloadable PDF to enhance its usability. Answer Records are Web-based content that are frequently updated as new information becomes available. Visit this Answer Record to obtain the latest version of the PDF.
This answer record primarily focuses on techniques to create test cases in simulation by forcing certain data patterns on core interfaces. When designing a system with IPs, such as PCI Express and Serial Rapid IO, designers may run into issues where the system halts due to a certain incoming packet or incorrect toggling of signals. To debug such issues in hardware could be difficult and time consuming, as this would need debugging tools such as ChipScope. The best option is to try to reproduce the issue in simulation by writing a specific testbench. The problem with this is you will need to write comprehensive code in the testbench to capture that particular use case scenario. This takes time and designers might not have enough time due to the critical nature of their project.
The pdf document provided with this answer record describes how a designer can drive custom packets on an interface of designs with PCI Express and Serial RapidIO cores with the force command in Verilog. force is a powerful Verilog command which you can use to drive signals at any timestamp of your simulation.