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AR# 538

XC7000, SYNOPSYS FPGA/Design Compiler - An example of a .synopsys_dc.setup file


Keywords: FPGA, Design Compiler, .synopsys_dc.setup

Urgency: Standard

General Description:
This answer contains an example of a .synopsys_dc.setup file for the XC7000 family
using Synopsys' Design Compiler or FPGA Compiler.


NOTE: For compiler to find the location of the XC7000 library, you MUST also have
the .synopsys_vss.setup file in this directory.

/* Design Compiler and FPGA Compiler startup file - .synopsys_dc.setup */
/* for XC7000 EPLD */

/* Insert actual $DS401 and $SYNOPSYS path into search_path below */

search_path = {. \
<DS401-XACT-Directory>/synopsys/libraries/syn \

link_library = {xc7000.db xc7000.sldb}
target_library = {xc7000.db}
symbol_library = {xc7000.sdb}
synthetic_library = {xc7000.sldb}

bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"

edifout_netlist_only = true
edifout_power_and_ground_representation = cell
edifout_write_properties_list = {LOC}

compile_fix_multiple_port_nets = true

xnfout_library_version = "2.0.0"

/* Useful aliases for EPLD design processing */

alias a analyze -format vhdl
alias e elaborate
alias c compile -map_effort low
alias sp set_port_is_pad
alias ip insert_pads
alias s set_attribute
alias wx write -format xnf -hierarchy -output
AR# 538
Date Created 08/31/2007
Last Updated 10/01/2008
Status Archive
Type General Article