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AR# 53828

Zynq-7000 AP SoC - What is the state of CPU1 after a software reset through SLCR.A9_CPU_RST_CTRL?


What is the state of CPU1 after applying a software reset to it?

The software reset operation is similar to the following:

mwr 0xf8000008 0xdf0d
mwr 0xf8000244 0x2
mwr 0xf8000244 0x22 mwr 0xf8000244 0x20 mwr 0xf8000244 0x0


According to the ARM documentation, when issuing the "CPU 1 software reset control" the CPU 1 will jump to address 0x0.

Only the SRST will force the bootROM to execute that will place CPU to 0xFFFFFF00 area and consequently to a WFE.

So, the user code needs to take the CPU 1 from 0x0 to the WFE in the 0xFFFFFF00 area.

The following memory write operations can make CPU1 go into a WFE state after a CPU1 software reset:

# write a stub into 0xffffff00
mwr 0xFFFFFF00 0xe3e0000f
mwr 0xFFFFFF04 0xe3a01000
mwr 0xFFFFFF08 0xe5801000
mwr 0xFFFFFF0C 0xe320f002
mwr 0xFFFFFF10 0xe5902000
mwr 0xFFFFFF14 0xe1520001
mwr 0xFFFFFF18 0x0afffffb
mwr 0xFFFFFF1C 0xe1a0f002
# write jump instruction into 0x0
mwr 0x00000000 0xe3e0f0ff
AR# 53828
Date Created 01/16/2013
Last Updated 07/11/2013
Status Active
Type General Article
  • Zynq-7000
  • EDK - 14.4
  • Processing System 7
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit