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AR# 53850

Vivado Constraints - Constraining the BUFGMUX - Clock MUXing


I have constrained my clocks, which are related or synchronous to each other.

I am seeing strange cross-clock violations that would never actually occur. 

What can I do to fix this?


The timing engine will  find any possible path between related clocks.  

Each of the create_clock XDC constraints have equal priority, so the tools do not use one exclusively. 

The tools require the user to specify that the clocks are not related. 

For Example:

A.  There are three clocks output from one MMCM (Clocks are 1x, 2x, and 4x the original clock frequency).

B. All of the logic in the design is being clocked by the output of the BUFGMUX. 
    The outputs of this MMCM are connected to two BUFGMUXs so that one of the three clocks can be selected.

C. Only one clock will be selected at a time to clock the designs logic, no true cross-clocking situations will occur. 
    Use the following command to physically separate the clocks:   

set_clock_groups -physically_exclusive -group clk_1x -group clk_2x -group clk_4x
Giving this information to Vivado allows the tool to analyze timing correctly.

More considerations in constraining exclusive clock groups are introduced in the Section "Overlapping Clocks Driven by a Clock Multiplexer" in (UG949).
AR# 53850
Date Created 01/17/2013
Last Updated 05/11/2015
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite