AR# 53854
Vivado Implementation - How do I debug Vivado routing issues?
Description
My design fails to route successfully.
What should I look for to resolve this issue?
Solution
When route fails to successfully route all/few of the signals, the root cause can be one of several things including:
- A component can be configured in such a way that it is unroutable.
- A component might be placed such that it is unroutable.
For example, if a clock IOB / BUFG component pair is not placed in a routable site pair.
The clock IOB component can route to the clock buffer if the IOB component is placed in a clock capable IOB site, that is located in the same half (TOP/BOTTOM) side of the device as the clock buffer.
- A design might also be unroutable due to congestion.
There might simply be too many connections in the design for the router to find a solution.
- A design could be unroutable due to over-constraining of timing.
The placement and routing decisions are a compromise between routability needs and timing needs.
If the timing needs are too heavily weighted, then the routability can suffer.
Debug technique:
Identify the unroutable net(s) involved
The router will have done one of several things:
1. Router ran to completion with one or a few unrouted nets without any warning messages about those nets.
The details about the routing can be found from the route status report file.
2. Router printed warning about unroutable nets and then ran to completion with one or a few unrouted nets.
Refer to the Place and route.log file for the warning messages.
Below is a list of the top 10 physical nodes with signal overlaps and upto 5 of the signals that were contending for this node resource:
1. Tile Name: INT_R_X113Y175 Node: FAN_ALT5 Overlapping Nets: 2
U_L2PP_CORE/PP_EG_VLAN_CAM_REFCLK0
U_L2PP_CORE/PP_IL_REFCLK1
2. Tile Name: INT_R_X113Y175 Node: FAN_BOUNCE5 Overlapping Nets: 2
U_L2PP_CORE/PP_EG_VLAN_CAM_REFCLK0
U_L2PP_CORE/PP_IL_REFCLK1
3. Router printed error messages and then stopped without attempting to complete the design.
Refer to Place and route.log file for the warning messages.
ERROR: [Route-3] Design is not routable as its congestion level is 7.
This failure is usually due to placer congestion and is beyond the scope of this Answer Record.
Examine the unrouted net in Device Editor
Open the implemented design in Vivado and find the list of unrouted nets using Find (refer to the below screen capture).
Highlight the unrouted nets and then zoom in on them to examine the pin connectivity involved.
After selecting the unrouted net, you can examine the connectivity in the net properties window as shown below:
Common issues to look for
- Carry Chains that are not aligned and BX pin not available for route-thru
- Too many global signals driving non-clock pins in a tile
- Differential I/O Pair not placed together in paired sites
- Clock Region over populated with too many global nets. No clock spines unused.
- Directed Route blocking switchbox route path to pin.
- BUFIO or BUFR with loads not constrained within reach
Linked Answer Records
Child Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 54795 | VIVADO IMPLEMENTATION - How can I fix Partial Antenna problems, [Drc 23-20] | N/A | N/A |
| AR# 53854 | |
|---|---|
| Date | 06/09/2015 |
| Status | Active |
| Type | General Article |
| Devices |
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| Tools |
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