Starting with the 7 Series FPGAs Memory Interface User Guide v1.6, the following DDR3 SDRAM Design Guideline is included:
- If multiple CK outputs are used, such as for dual rank, all CK outputs must come from the same byte lane.
This answer record details this pin restriction.
Important Note: Using the default "New Design" flow, MIG 7 Series has followed this CK pin placement rule since the first officially supported release for dual rank, v1.6.
However, when using the "Fixed Pin-Out" or "Verify Pin Changes and Update Design" flow, the DRC check against this rule was not included in MIG 7 Series until v1.8 .
Because of this, when using one of these two flows, incorrect pin-outs may have been verified and generated by MIG 7 Series allowing CK pins to be in separate byte groups.
Starting with MIG 7 Series v1.8, the correct DRC checks are included.
All DDR3 Dual Rank MIG 7 series pin-outs should be validated using v1.8.