We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5390

FPGA Express: Warning: No global set/reset (GSR) net can be used in the design .. (FE-GSRMAP-8)


Keywords: FE, GSRMAP-8 , global set / reset, GSR

Urgency: Standard

General Description
When synthesizing a design using FPGA Express, the following warning may be issued:

Warning: No global set / reset (GSR) net could be used in the design because
the design contains the unlinked cell '/<design>-Optimized/<module>'. (FE-GSRMAP-8)

This warning may occur when you instantiate a black box in your design. The black box
can be a LogiBLOX or Coregen module, or any netlist that has not been read into the
FPGA Express project. Because FPGA Express has no knowledge of the synchronous
elements in the black box, it will be unable to determine if there is a single set/reset signal
for the entire design, and will therefore not be able to infer the STARTUP module that will
address the Global Set/Reset needs of the design.


Two possible solutions exist.

The first is to instantiate the STARTUP module. Simply connect your global set/reset
signal to the GSR pin of STARTUP, and Express will not have to worry about inferring
this component. Note that you will still see the Express warning message when you do this, but the GSR will indeed be utilized. You can verify this by checking the map report.

The other option is to tell FPGA Express to ignore black boxes when inferring STARTUP.
This is done under the Xilinx Options tab of the Express Constraints Editor. If you check
the box next to "Ignore unlinked cells during GSR mapping", the FPGA Express will only
worry about the set/reset signals connected to synchronous elements that it has access to.
AR# 5390
Date Created 01/12/1999
Last Updated 08/11/2003
Status Archive
Type General Article