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AR# 53903

7 Series - When the Readback CRC and AES bitstream encryption features are both enabled, the Readback CRC requires the ICAP to be included in the design to function.


When the Readback CRC (POST_CRC) and AES bitstream encryption features are both enabled, the Readback CRC will not be operational unless the ICAP is instantiated and a clock is provided.

Software prior to ISE Design Suite 14.5 and Vivado Design Suite 2013.1 will not catch this limitation. 


Readback CRC requires the ICAPE2 to be instantiated to function.

The ICAP clock is required to clock the Readback CRC functionality.

For more information on the ICAP, consult the 7 Series FPGAs Configuration User Guide (UG470).

For details on how to instantiate the ICAPE2 see the Xilinx 7 Series FPGA Libraries Guide for HDL Designs (UG768).

A check for this condition will be added in Vivado 2013.1 and ISE Design Suite 14.5.
AR# 53903
Date Created 02/06/2013
Last Updated 11/28/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
  • ISE Design Suite - 14.3
  • More
  • ISE Design Suite - 14.4
  • ISE Design Suite - 13
  • Vivado Design Suite - 2012.4
  • Vivado Design Suite - 2012.3
  • Vivado Design Suite - 2012.2
  • Vivado Design Suite - 2012.1
  • Less