AR# 53919 Design Advisory for MIG 7 Series v1.8 RLDRAM II - Pinout violation not detected in "Fixed Pin Out" mode or "Verify Pin Changes and Update Design" flow
Description
Version Found: v1.8
Version Resolved and other Known Issues: See (Xilinx Answer 45195)
7 series architecture requires that for given byte lane, the DQSCC_N location is used to generate the 3-state control signal. RLDRAM II designs require that the DQSCC_N location in the same byte lane as data must be unused or can be shared with QVLD, DK#, or DM.This requirement is met by MIG 7 series v1.8 when using the Create Design flow and Bank Selection mode shown below:
AR53919.png
However, when using the "Fixed Pin Out" mode or the "Verify Pin Changes and Update Design" flow usersmust ensure this requirement is met manuallyas theviolation is not detected properly using these flows.
Solution
If this pinout requirement is not met, designs will fail in both behavioral simulation and hardware simulations during calibration, as a result of the3-state control for the bi-directional data bits will not function properly.
There isno workaroundavailable, as the DQSCC_N location for 3-state control is a dedicated route in the 7 series architecture. The pinout requirement must be met.
Revision History
01/24/2012 - Initial Release
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45195 | MIG 7 Series - Release Notes and Known Issues for All Versions | N/A | N/A |