Following VHDL/Verilog syntax examples as mentioned in XST will be supported by Vivado Synthesis,
VHDL example,
attribute shreg_extract : string;
attribute shreg_extract of {signal_name |entity_name }: {signal|entity} is "{yes|no},(true|false}";
Verilog Syntax Example
Placing before the module or signal declaration,
(* shreg_extract = "{yes|no}, {true|false}" *)
However, there is a caveat. The SRL inference happens near the end of the synthesis flow. If the user sets the attribute on a module and this module is flattened, then the attribute is lost. So, it definitely works if you have flatten_hierarchy=none, but may not work for full or rebuilt. It is not difficult to tweak the code to make it work for top level module, meaning if you set it on the top level module, it then works as a global switch.
SHIFT REGISTER THRESHOLD:
Option:1
In ISE you can set how many registers there are allowed before it will convert them to SRL.
Vivado synthesis does not have an option today equivalent to XST either via global GUI switch or via HDL attributes. There is a plan to accommodate this feature in 2013.2.
In the meantime, Vivado synthesis does support following parameter that can be added via Tcl,
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter srlDepthThreshold 3"
The number is an integer from 2 and up.
Option: 2
Another option to disable this behavior is to apply attribute (* shreg_extract = "no" *) to the affected registers.