Solution

General Information

Supported Devices can be found in the following locations:

• MIG 7 Series IP Page: http://www.xilinx.com/products/technology/memory-interfacing/
• Open the Vivado software -> IP Catalog, right click on an IP and select "Compatible Families"

Note: For a complete part and package support list, open the Vivado software -> IP Catalog, right-click on an IP and select "Compatible Families"

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Core Version	Vivado Tools Version
v1.9a	2013.1
v1.8a	2012.4
v1.7a	2012.3
v1.6	2012.2
v1.5	2012.1

For a list of supported memory interfaces and features for 7 series FPGAs, see the 7 Series FPGAs Memory Interface Solution Data Sheet (DS176) and 7 Series FPGAs Memory Interface Solution User Guide (UG586) located at:
http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_meminterfacecontrol_mig-7series.htm

For a list of supported frequencies for 7 series FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the 7 Series Documentation Center. The MIG tool includes the appropriate frequency range for each specific memory interface configuration

Table 2 provides answer records for general guidance when using the MIG 7 Series core.

Table 2: General Guidance

Answer Record	Title
(Xilinx Answer 34243)	Xilinx MIG Solution Center
(Xilinx Answer 43879)	7 Series MIG DDR3 - Hardware Debug Guide
(Xilinx Answer 33566)	Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
(Xilinx Answer 42944)	Design Advisory Master Answer Record for Virtex-7 FPGA
(Xilinx Answer 42946)	Design Advisory Master Answer Record for Kintex-7 FPGA
(Xilinx Answer 42665)	MIG 7 Series - Why does the MIG Example Design fail in BitGen?
(Xilinx Answer 42036)	MIG 7 Series- Internal/External Vref Guidelines
(Xilinx Answer 40603)	MIG 7 Series DDR3/DDR2 - Clocking Guidelines

 

Table 3: List of Memory Devices Supported

	Components	RDIMMs	UDIMMs	SODIMMs
DDR3 SDRAM	MT41J128M8XX-125/15E	MT9JSF25672PZ-1G6/1G4	MT9JSF25672AZ-1G9/1G6/1G1	MT8KTF51264HZ-1G9
	MT41J64M16XX-125G/15E	MT9KSF25672PZ-1G4	MT8JTF51264AZ-1G6/1G4	MT8JTF12864HZ-1G6/1G4
	MT41J256M8XX-107/125/15E/187E	MT18JSF25672PDZ-1G6	MT8JTF12864AZ-1G6/1G4	MT8JTF25664HZ-1G4/1G1
	MT41J128M16XX-107G/125/15E/187E	MT18JSF51272PDZ-1G4/1G6	MT8JTF25664AZ-1G4	MT8KTF51264HZ-1G9/1G6
	MT41J512M8XX-107/125/15E	MT9HTF12872PZ-80E	MT8KTF51264AZ-1G6/1G4	MT8KTF25664HZ-1G6/1G4
	MT41J256M16XX-107/125/15E	MT9HTF12872PZ-667	MT8KTF25664AZ-1G4/1G6	MT8KSF25664HZ-1G4
	MT41K256M8XX-125/15E	MT9KSF51272PZ-1G4	MT9HTF12872AZ-80E	MT8KTF12864HZ-1G9
	MT41K128M16XX-15E	MT18KSF1G72PDZ-1G6/1G4	MT9KSF25672AZ-1G6/1G4	MT16JTF25664HZ-1G4/1G6
	MT41K512M8XX-107/125/15E		MT16JTF51264AZ-1G4	MT16JTF51264HZ-1G4
	MT41K256M16XX-107/125/15E		MT18JSF25672AZ-1G4	MT8JSF25664HDZ-1G4
			MT18JSF51272AZ-1G6	MT18KSF1G72HZ-1G6
			MT8HTF12864AZ-800	MT18KSF51272HZ-1G4
			MT8HTF25664AZ-800	MT8HTF12864HZ-800
				MT8HTF25664HZ-800
				MT4KTF25664HZ-1G9
				MT8KTF51264HDZ-1G6
DDR3L SDRAM	MT41K512M8THD-15E		MT16KTF51264AZ-1G4	MT16KSF51264HZ-1G4
	MT41K256M32SLD-125E		MT16KTF51264AZ-1G6	MT16KTF51264HZ-1G4
			MT18KSF51272AZ-1G4	MT16KTF51264HZ-1G6
				MT4KTF25664HZ-1G9
				MT8KTF51264HDZ-1G6
DDR2 SDRAM	MT47H128M16XX-25E	MT9HTF12872PZ-80E	MT8HTF12864AZ-800	MT8HTF12864HZ-800
	MT47H128M8XX-25/25E	MT9HTF12872PZ-667	MT8HTF25664AZ-800	MT8HTF25664HZ-800
	MT47H256M8XX-25E	MT18HTF25672PZ-667	MT9HTF12872AZ-80E
	MT47H64M16XX-25/25E
	MT47H512M8WTR-25E
	MT47H64M16HR-25E
QDRII+ SRAM	K7S3236T4C-FC45
	K7S3218T4C-FC45
	CY7C15632KV18-500BZC
	CY7C1565KV18-500BZC
	CY7C25632KV18-500BZC
	CY7C2565KV18-500BZC
	CY7C2263KV18-550BZXI
	CY7C2265KV18-550BZC
	CY7C2163KV18-550BZXI
	CY7C2165KV18-550BZC
	CY7C25632KV18-450BZC
	CY7C2565KV18-450BZC
	CY7C25442KV18-333BZI*
	CY7C2264XV18-450BZXC*
	CY7C2262XV18-450BZXC*
	CY7C2564XV18-450BZXC*
	CY7C2562XV18-450BZXC*
	CY7C2563KV18-500BZC/450BZC
	CY7C25652KV18-500BZC/450BZC
RLDRAM II	MT49H16M36XX-18/25E/25/33
	MT49H32M18XX-18/25E/25/33
	MT49H8M36XX-25/33
	MT49H16M18XX-25/33
RLDRAM III	MT44K16M36XX-125
	MT44K16M36XX-125E
	MT44K32M18XX-125
	MT44K32M18XX-125E
	MT44K32M36XX-125
	MT44K32M36XX-125E
LPDDR2	MT42L128M16D1KL-25-IT/3-IT
	MT42L64M32D1KL-25-IT/3-IT
	MT42L256M16D1LG-25-WT
	MT42L128M32D1LG-25-WT

  *Components for Burst Length 2

Known and Resolved Issues

The following table provides known issues for the MIG 7 Series core, starting with v1.9a, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

MIG 7 Series DDR3/DDR2 SDRAM

The following table provides known issues for MIG 7 series DDR3/DDR2 SDRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record	Title	Version Found	Version Resolved
(Xilinx Answer 55192)	MIG 7 Series - Using ChipScope in Vivado	1.9a	Not Resolved
(Xilinx Answer 54584)	MIG 7 Series - Needed XDC constraint changes when using a Synplify netlist within Vivado	1.8.a	Not Resolved
(Xilinx Answer 52176)	MIG 7 Series DDR3 - 48-bit design unable to fit into 2 HP banks	1.6	Not Resolved
(Xilinx Answer 55134)	MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure	1.5	Not Resolved
(Xilinx Answer 53433)	MIG 7 Series DDR3/DDR2 - MAX_FANOUT attribute not being honored	1.8.a	Not Resolved
(Xilinx Answer 53435)	MIG 7 Series DDR3/DDR2 - Timing violations may be seen in 2:1 designs running around 533MHz within u_ddr_mc_phy	1.8.a	Not Resolved
(Xilinx Answer 54384)	MIG 7 Series DDR3 - changing DATA_PATTERN in sim_tb_top.v does not work as expected	1.8.a	Not Resolved
(Xilinx Answer 54710)	MIG 7 Series - DDR3 - Controller hangs on a read-modify-write operation	1.8.a	Not Resolved
(Xilinx Answer 55040)	MIG 7 Series - DDR3, LPDDR2, and DDR2 support changes for Virtex-7 HT devices	1.9.a	N/A
(Xilinx Answer 55056)	MIG 7 Series DDR2/DDR3 - AXI Interface Enabled - During continuous read or write commands, bubbles/gaps are seen between the user interface bursts	1.8.a	Not Resolved
(Xilinx Answer 55060)	MIG 7 Series DDR3/DDR2 - AXI Interface Enabled - Controller services write command before read is completed.	1.8.a	Not Resolved

 

MIG 7 Series QDRII+ SRAM

The following table provides known issues for MIG 7 series DDR3/DDR2 SDRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record	Title	Version Found	Version Resolved
(Xilinx Answer 55192)	MIG 7 Series - Using ChipScope in Vivado	1.9a	Not Resolved
(Xilinx Answer 54942)	MIG 7 Series QDRII+ - ADDR_CTL_MAP parameter width incorrect when 4 addr/ctrl bytes used	1.8.a	Not Resolved
(Xilinx Answer 54338)	MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection	1.8.a	Not Resolved
(Xilinx Answer 55134)	MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure	1.5	Not Resolved
(Xilinx Answer 55129)	MIG 7 Series+ - Cypress memory model fails simulation for designs with Burst Length{BL} = 2 and Data Width = 18	1.5	Not Resolved

MIG 7 Series RLDRAMII

The following table provides known issues for MIG 7 series DDR3/DDR2 SDRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record	Title	Version Found	Version Resolved
(Xilinx Answer 55192)	MIG 7 Series - Using ChipScope in Vivado	1.9a	Not Resolved
(Xilinx Answer 55146)	MIG 7 Series RLDRAM II - timing error due to high net delay in Vivado implementation	1.9.a	Not Resolved
(Xilinx Answer 55138)	MIG 7 Series RLDRAM II - incorrect error message for data mask pin allocation when verifying pin out in MIG GUI	1.9.a	Not Resolved
(Xilinx Answer 54338)	MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection	1.8.a	Not Resolved
(Xilinx Answer 55134)	MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure	1.5	Not Resolved

MIG 7 Series RLDRAM3

The following table provides known issues for MIG 7 series DDR3/DDR2 SDRAM.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record	Title	Version Found	Version Resolved
(Xilinx Answer 55192)	MIG 7 Series - Using ChipScope in Vivado	1.9a	Not Resolved
(Xilinx Answer 54338)	MIG 7 Series QDRII+/RLDRAMII/3 - PDRC-25 Advisory message on ILOGIC / OLOGIC connection	1.8.a	Not Resolved
(Xilinx Answer 52231)	MIG 7 Series RLDRAM 3 - Data Mask pins must be placed in the same byte lane as their corresponding data bytes	1.7.a	Not Resolved
(Xilinx Answer 55134)	MIG 7 Series - all interfaces have pll_locked and not mmcm_locked tied to their reset structure	1.5	Not Resolved

Revision History
4/3/2013 - Initial release