Solution

54139-1.jpg

1. Switch / Jumper Settings
2. Board Power
3. Cable detection
4. JTAG Initialization

The following debug steps assume steps 1-4 have been checked and are working:
5. JTAG Configuration
6. Master SPI Configuration
7. XADC
8. PCIe
9. IBERT
10. DDR3
11. Ethernet
12. Interface Tests
13. Known Issues for AC701


1. Switch / Jumper Settings:

Default Switch and Jumper Settings for the AC701 are:

Start from a known safe scenario by verifying the default Switch and Jumper settings. You can then set switches / jumpers for your application.

a. User GPIO DIP Switch SW2:

54139-2.jpg

54139-3.jpg
b. Configuration DIP Switch SW1:

54139-4.jpg
The default mode setting M[2:0] = 001 selects Master SPI configuration at board power-on.
To configure the XC7A200T device in this mode, an image must be loaded in the QSPI flash (U7) on the board.

54139-5.jpg
c. Default Jumper Settings:

54139-6.jpg
d. Default XADC Jumper Settings:

54139-7.jpg
e. Default SFP Settings:

54139-8.jpg
f. Default PCIe Lane Select Settings:

54139-9.jpg



2. Board Power

Note: Power-ON LEDs: Initial power testing is performed on the bench using the AC-to-DC power adapter provided in the AC701 Evaluation Kit. The status of Power-ON LEDs is an indication of board health.

a. Check the status of the following LEDs at Power-ON:

54139-12.jpg

54139-13.jpg
b. If these LEDs above are not lit at power on, you may need to reprogram the TI Power Controllers on your board. This can be done using the Texas Instruments Fusion Digital Power Manufacturing tool software package, the Texas Instruments USB Interface Adapter EVM, and the appropriate XML script.
Please see (Xilinx Answer 37561) for more details; open a Webcase with Xilinx Technical Support to receive the appropriate XML files (these are board specific).
If you do not have a TI USB Interface Adapter EVM, you can follow the steps in (Xilinx Answer 54022) to order one at a significant discount.
c. If 12V Power LED (DS22) is not Green, then 12VDC is not being delivered to the AC701 power input connector. Follow these steps:

54139-10.jpg



3. Cable detection

The AC701 uses a USB-to-micro-B cable plugged into the AC701 Digilent USB-to-JTAG module, U26.
Atwo mm JTAG header (J4) is also provided in parallel for access by Xilinx download cables, such as the Platform Cable USB II and the Parallel Cable IV.
If you have access to a number of different cables, it is recommended that you attempt detection with each of these cables before moving on to create a Webcase.

a. USB A-to-micro-B cable
i. Is the cable visible in Device Manager? If thethree items highlighted in the figure below are visible in Device Manager, this confirms that your USB cable is operational and has been correctly identified.

51233-18.jpg
ii. Are cable drivers loaded correctly? Drivers for this cable should be included in the iMPACT installation. However, if problems are experienced with USB A-to-micro-B cable connection, a Digilent plug-in can be downloaded from the link below.
For installation, please follow the guidelines in the document provided in the downloaded files:
http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN.
This plug-in requires Adept systems 2.4 or later for Windows and Adept systems 2.3.9 or later for Linux. Adept software is available from Digilent:
http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2.
iii. Check system properties & environment variables. For information on environment variables, please see (Xilinx Answer 11630).
iv. Is the USB port enabled? (User can reboot their computer to re-initialize their USB buses)
v. Are Xilinx tools correctly installed? (iMPACT or ChipScope Pro) If an issue is suspected with tools installation, please see Installation and Licensing Guide (make sure to use the most recent version of tools, and associated documentation, which supports the AC701)
vi. Is the Operating System (OS) being used Windows 7? If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).

b. Platform Cable USB II
i. Is the cable visible in Device Manager?

54139-17.jpg
ii. Are the cable drivers loaded correctly? Drivers for this cable should be included in the iMPACT installation. However, if problems are experienced with Platform Cable USB II connection, please follow the uninstall and reinstall instructions in (Xilinx Answer 44397).
iii. Check system properties & environment variables. For information on environment variables, please see (Xilinx Answer 11630).
iv. Is the USB port enabled?
v. Are Xilinx tools correctly installed? (iMPACT or ChipScope Pro)
vi. Is the Operating System (OS) being used Windows 7? If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).

c. Parallel Cable IV
i. Are the cable drivers loaded correctly? See (Xilinx Answer 9984) for more information.
ii. If you receive the following message in iMPACT: "ERROR: Device Control LPT_WRITE_CMD_BUFFER Failed" see (Xilinx Answer 22293).
Note: Parallel Cable IV speed cannot be modified in iMPACT 13.x and 12.x - see (Xilinx Answer 41808) for more details.
iii. If you cannot establish a connection with the Parallel Cable IV, see (Xilinx Answer 15742).

If the above steps fail to enable you to connect, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



4. JTAG Initialization

The status of the board JTAG chain is checked using Xilinx Tools (iMPACT or ChipScope Pro). To check to see that the JTAG chain is initialized correctly, follow this JTAG Initialization Test Case:

a. Remove any FMC cards from AC701
b. Set the mode switch SW1 for JTAG mode (101)
c. Power up AC701 on the bench (not in a chassis)
d. Connect the Digilent USB A-to-micro-B cable to the AC701 (through the Digilent onboard USB-to-JTAG configuration logic module - U26)
e. Check Digilent device shows up in Device Manager
f. Ensure Xilinx tools (Vivado 2012.3 or later - preferably the latest version of tools that support the AC701) are correctly installed
g. Launch iMPACT - is the cable identified correctly?
i. If not, see section 3. Cable detection above.
ii. If yes, but iMPACT did not discover and display the JTAG chain, slow down the cable speed (Output > Cable Setup)
iii. If yes, but iMPACT did not discover and display the JTAG chain, and slowing down the cable speed does not resolve the issue, see the following (assumes Digilent USB A-to-micro-B cable is plugged into USB-to-JTAG configuration logic module U26):

54139-11.jpg

If the above steps fail to enable you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC. Connect the Platform Cable USB to header J4, and connect to your PC.
Ensure Xilinx tools (Vivado 2012.3 or later - preferably the latest version of tools that support the AC701) are correctly installed. Launch iMPACT - is the cable identified correctly?

If the above steps fail to enable you to initialize the JTAG chain, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



5. JTAG Configuration

If JTAG chain initializes OK, but JTAG configuration fails, check the following:

a. Verify the mode switch settings for JTAG configuration mode:

54139-14.jpg
b. In iMPACT, select a lower cable frequency (Output > Cable Setup) and re-attempt configuration
c. In iMPACT, run the Chain Integrity test by selecting Debug > Chain Integrity Test. iMPACT will assist in the debugging of this scenario by providing insight into where the failing connection in the chain could be.
d. Pulse the PROG push button on the AC701 (SW9). Pulsing PROG will clear out any problems caused by power up ramp rate issues to the FPGA.
e. Read back the Status Register in iMPACT (Debug > Read Status Register). The information extracted from the Status Register can help determine the stage of configuration and where a failure has occurred. See (Xilinx Answer 24024) for more details.
f. Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center. The Configuration Solution Center is available to address all questions related to Configuration.

If the above steps fail to enable JTAG configuration, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



6. Master SPI Configuration

The iMPACT software tool can be used to indirectly program the QSPI flash memory (U7) on the AC701.

a. To confirm the SPI interface on the board is working using a known working example design, download and run the AC701 Restoring Flash Contents Design Files, whichever version is appropriate for your silicon and software version.
It is recommended to always use the latest version of software which supports the AC701, and the associated version of the AC701 Restoring Flash Contents Design Files.
Follow the associated PDF. All are available from the AC701 Example Designs page.
AC701 Restoring Flash Contents Design Files: rdf0226.zip
AC701 Restoring Flash Contents PDF: xtp228.pdf
To identify the silicon version of your kit, please see (Xilinx Answer 37579).
Read the AC701 Restoring Flash Contents design document: AC701 Restoring Flash Contents PDF: xtp228.pdf (Vivado) and follow the instructions therein.

b. If you have loaded an .mcs file into the SPI flash on the AC701, and subsequent Master SPI configuration of the Artix-7 fails, the following points should be checked:

i. If the ".mcs" file is correctly loaded, you will see the FPGA and the FLASH device in the JTAG chain, as shown here:

54139-16.jpg
If you do not see the FLASH device attached to the xc7a200t as shown, see the iMPACT Help section of ISE Help.
ii. Verify the mode switch settings for Master SPI configuration:

54139-15.jpg
iii. In iMPACT, select a lower cable frequency and re-attempt configuration.
iv. Pulse the PROG push button on the AC701 (SW9), to attempt to reload the FPGA with the configuration image.
v. Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center. The Configuration Solution Center is available to address all questions related to Configuration.

If the above steps fail to enable SPI configuration, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



7. XADC

a. Verify XADC jumper settings - see Section 1. Switch / Jumper Settings, part d, above.
b. Ensure Xilinx tools (latest version which supports AC701) are correctly installed on your machine.
c. To test the XADC interface on the AC701, use a known working reference design. If you have access to the AMS101 Evaluation Card (shown below) with the AC701, download and run the Artix-7 FPGA AC701 Evaluation Kit AMS Targeted Reference Design (latest version) to check the XADC functionality.

50079-23.jpg
Please ensure you have the correct version of Vivado Design Suite installed to run this TRD. It is recommended to always use the latest version of software, TRD, and associated documentation (7 Series FPGA AMS Targeted Reference Design User Guide).
You can download this Targeted Reference Design, as well as the AMS Evaluator Installer and Documentation for this TRD, from the AC701 Documentation page.
d. Details on XADC operation can be found in UG480 and UG772. (Be sure to use the most recent version of the document)

If the above steps fail to resolve the XADC issue, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



9. PCIe

If the AC701 configures correctly, however the PCIe interface does not operate as expected, check the following:

a. Do NOT plug a PC ATX power supply 6-pin connector into J49 on the AC701 board. The ATX 6-pin connector has a different pinout than J49. Connecting an ATX 6-pin connector into J49 will damage the AC701 board and void the board warranty.
To install and power the board correctly, follow the instructions given in UG952 AC701 Evaluation Board User Guide - Appendix D - Board Setup.
b. If you are using a Z77 (Ivy Bridge) platform, and are attempting to run the AC701 Targeted Reference Design, please see (Xilinx Answer 53489) - Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform.
c. Check J12, the lane width, is set correctly.
d. See (Xilinx Answer 40469) - 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions for Known Issues affecting 7-Series, including Artix-7.
e. Download and run the AC701 PCIe Example Design, whichever version is appropriate for your silicon and software version. It is recommended to always use the latest version of software which supports the AC701, and the associated version of the AC701 PCIe Example Design.
Follow the associated PDF. All are available from theAC701 Example Designs page.
AC701 PCIe Design Files: rdf0225.zip
AC701 PCIe PDF: xtp227.pdf
To identify the silicon version of your kit, please see (Xilinx Answer 37579).
f. Read the AC701 PCIe design document: AC701 PCIe PDF: xtp227.pdf (Vivado) and follow the instructions therein.

If the above steps fail to resolve the PCIe issue, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



10. IBERT

NOTE: Running IBERT requires the installation of ChipScope tool. A device-locked license for this software is provided with the Artix-7 FPGA AC701 Evaluation Kit.
If the AC701 configures correctly, however IBERT does not operate as expected, check the following:

a. If using MGT loopback, ensure you have the correct equipment, including SMA cables, SMA Quick connects and Connect Optical Loopback Adapter:

50079-21.jpg
50079-20.jpg
50079-22.jpg

More information can be found in the AC701 GTP IBERT PDF from the AC701 Example Designs page.
b. Download and run the AC701 GTP IBERT Example Design, whichever version is appropriate for your silicon and software version. It is recommended to always use the latest version of software, and associated version of the AC701 GTP IBERT Example Design.
Follow the associated PDF. All are available from the AC701 Example Designs page.
AC701 GTP IBERT Design Files: rdf0222.zip
AC701 GTP IBERT PDF: xtp224.pdf
To identify the silicon version of your kit, please see (Xilinx Answer 37579).
c. Read the AC701 GTP IBERT Example Design document: AC701 GTP IBERT PDF: xtp224.pdf (Vivado) and follow the instructions therein.
d. IBERT Design Assistant: (Xilinx Answer 45562).

If the above steps fail to resolve the IBERT issue, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



11. DDR3

The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM). The SODIMM socket has a perforated EMI shield surrounding it.
If a problem is suspected with DDR3 / MIG, check the following:

a. Ensure DDR3 SODIMM module is inserted correctly.
b. Download and run the AC701 MIG Example Design, whichever version is appropriate for your silicon and software version. It is recommended to always use the latest version of software, and associated version of the AC701 MIG Example Design.
Follow the associated PDF. All are available from the AC701 Example Design page.
AC701 MIG Design Files: rdf0223.zip
AC701 MIG PDF: xtp225.pdf
To identify the silicon version of your kit, please see (Xilinx Answer 37579).
c. Read the AC701 MIG Example Design document: AC701 MIG PDF: xtp225.pdf (Vivado) and follow the instructions therein.
d. Review (Xilinx Answer 34243) - Xilinx MIG Solution Center. The MIG Solution Center is available to address all questions related to the Memory Interface Generator (MIG).

If the above steps fail to resolve the DDR3 issue, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



12. Ethernet

The AC701 uses the Marvell Alaska PHY device (88E1116R) at U12 for Ethernet communications at 10 Mb/s, 10 Mb/s, or 1,000 Mb/s. The board supports RGMII mode only.
The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01ERJ-45 connector (P4) with built-in magnetics.
If a problem is suspected with Ethernet on the AC701, check the following:

a. Download and run the AC701 Ethernet Example Design, whichever version is appropriate for your silicon and software version. It is recommended to always use the latest version of software, and associated version of the AC701 Ethernet Example Design.
Follow the associated PDF. All are available from the AC701 Example Design page.
AC701 Ethernet Design Files: rdf0221.zip
AC701 Ethernet PDF: xtp223.pdf
To identify the silicon version of your kit, please see (Xilinx Answer 37579).
b. Read the AC701 Ethernet Example Design document: xtp223.pdf (Vivado) and follow the instructions therein.
c. Review (Xilinx Answer 38279) - Ethernet IP Solution Center. The Ethernet IP Solution Center is available to address all questions related to the Xilinx solutions for Ethernet IP.

If the above steps fail to resolve the Ethernet issue, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



13. Interface Tests

(Xilinx Answer 54383) - Artix-7 FPGA AC701 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the AC701 are working correctly. This answer record forms part of (Xilinx Answer 43748) - Xilinx Boards and Kits Debug Assistant.
If the above tests fail to resolve the issue, please open a Webcase to further debug the problem.
In the Webcase notes, please include all debug steps taken to date.



14. Known Issues for AC701

All Known Issues for the Artix-7 FPGA AC701 Evaluation Kit are listed in (Xilinx Answer 51900) - Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record.
If the issue you are faced with is not listed in this Answer Record, and debug fails to resolve the issue, please open a Webcase to further debug the problem.