We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54160

Vivado HLS - do not use __SYNTHESIS__ on top level module ports.


If __SYNTHESIS__ is used to guard or mask some of the top level ports of the C function, the simulation and co-simulation might not match.


The __SYNTHESIS__ macro is automatically defined by Vivado HLS when synthesis is performed.

This macro is defined during the High-Level Synthesis and ports will be generated accordingly.

However, the macro is not defined during C simulation and as a result, you might not be able to properly test your designs.

The simulation and co-simulation may mismatch as the generated software and hardware may mismatch in terms of ports, numbers and names.

It can lead to a crash in the co-simulation with or without messages.

As a result it is preferable to not use __SYNTHESIS__ on the top level ports.

AR# 54160
Date Created 02/06/2013
Last Updated 02/20/2015
Status Active
Type General Article
  • Vivado Design Suite
  • AutoESL