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AR# 54249 IP Release Notes and Known Issues for LogiCORE RXAUI for Vivado 2013.1 and Forward

Description

This answer record contains the Release Notes and Known Issues for the RXAUI Core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE RXAUI Core IP Page:
http://www.xilinx.com/products/intellectual-property/RXAUI.htm

Solution

General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
 
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
Core Version Vivado Tools Version
v3.0 2013.1
v2.4 2012.3
v2.3 2012.1
 
General Guidance
The table below provides Answer Records for general guidance when using the LogiCORE RXAUI core.
Article Number Article Title
(Xilinx Answer 38279) Ethernet IP Solution Center
(Xilinx Answer 55077) Ethernet IP Cores - Design Hierarchy in Vivado
(Xilinx Answer 55078) RXAUI Shared Clocking and Reset Logic
(Xilinx Answer 55079) RXAUI Debug Interface 
 
 
Known and Resolved Issues
The following table provides known issues for the RXAUI core, starting with v3.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Article Number Article Title Version Found Version Resolved
(Xilinx Answer 55229) Artix 7 - Critical Warning - No cells match DRP path for false path constraint v2.4 Workaround in AR
(Xilinx Answer 55009) 7 Series GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode v2.4 v3.0
(Xilinx Answer 53561) Artix-7 - RX Reset Sequence Requirement for Production Silicon  v2.4 v3.0
(Xilinx Answer 50848) 7 Series GT Transceivers - Updates maybe needed to GT wrapper files v2.4 v3.0
 
Revision History:
04/03/2013 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
55078 RXAUI v3.0 - 2013.1 - Shared Clock and Reset Logic N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
55077 Ethernet IP - Design hierarchy in Vivado tools N/A N/A
55229 LogiCORE RXAUI v3.0 - Vivado - Artix-7 Devices - Critical Warning - No cells match DRP path for false path constraint N/A N/A
55079 RXAUI v3.0 - 2013.1 - Debug Interface N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
55009 Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode N/A N/A
53561 Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon N/A N/A

Actions

AR# 54249
Date Created 04/01/2013
Last Updated 04/01/2013
Status Active
Type Release Notes
IP
  • RXAUI
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