This answer record contains the Release Notes and Known Issues for the Tri-Mode Ethernet MAC Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Tri-Mode Ethernet MAC Core IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|v9.0 (Rev. 11)||2018.1|
|v9.0 (Rev. 10)||2017.4|
|v9.0 (Rev. 9)||2017.3|
|v9.0 (Rev. 8)||2017.2|
|v9.0 (Rev. 7)||2017.1|
|v9.0 (Rev. 6)||2016.3|
|v9.0 (Rev. 5)||2016.2|
|v9.0 (Rev. 3)||2015.4|
|v9.0 (Rev. 2)||2015.3|
|v9.0 (Rev. 1)||2015.2|
|v8.3 (Rev. 1)||2014.4|
|v8.2 (Rev. 2)||(Xilinx Answer 61328)|
|v8.2 (Rev. 1)||2014.2|
|v7.0 (Rev. 1)||(Xilinx Answer 57446)|
The table below provides answer records for general guidance when using the Tri-Mode Ethernet MAC LogiCORE IP.
|(Xilinx Answer 38279)||Ethernet IP Solution Center|
|(Xilinx Answer 55077)||Ethernet IP Cores - Design Hierarchy in Vivado|
Known and Resolved Issues
The following table provides known issues and resolved issues for the Tri-Mode Ethernet MAC core, starting with v6.0, initially released in the Vivado 2012.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|NA||Fixed bug in AVB RTC clock logic which results in the he RTC clock second and nano-second fields being out of sync when the nano-second field rolls over
|NA||Fixed bug in Demo testbench for 2.5G, which wrongly flagged an frame check error during user injected error
|(Xilinx Answer 67273)||Tri-Mode Ethernet MAC v9.0 (Rev.4) - 63-byte frames are not counted correctly||v9.0 (Rev. 4)||See Answer Record|
|NA||Fixed bug in 1G Example Design Pattern Generator module, VHDL version, in which the output frames were of incorrect size.||v9.0 (Rev.1)
|NA||Fixed corner case Statistics bug - RX Undersize Frames counter and RX Fragment Frames counter not incrementing correctly in absence of preamble bytes||v9.0 (Rev.2
|NA||Fixed corner case bug in transmit logic - MAC might lose input frame bytes in cases where user initiates a back-to-back frame transfer and asserts error at very early stages of frame transmission||v9.0 (Rev.2
|NA||Fixed corner case bug in 2.5G transmit logic - MAC might not corrupt the TX frame if the user error indication is received at very early or very late stages of frame transmission||v9.0 (Rev.2)
|(Xilinx Answer 65947)||LogiCORE Tri Mode Ethernet MAC v9.0 (Rev 3) - UltraScale Plus Devices - GMII/RGMII - Timing not met on I/O Interface||v9.0||See Answer Record|
|(Xilinx Answer 64242)||Tri-Mode Ethernet MAC v9.0 - The core currently does not meet timing on 2.5G designs for -2L and -1LV devices||v9.0||See Answer Record|
|(Xilinx Answer 63906)||Tri-Mode Ethernet MAC v9.0 - TEMAC might stop working if only the 10/100 license is installed in Vivado 2015.1||v9.0||See Answer Record|
|(Xilinx Answer 61328)||MDIOREADY can go high before MDIO RX DATA updates||v8.2||v8.3|
|(Xilinx Answer 62021)||Simulation - 'X' seen on AXI-Lite Bus strobes||v8.2||v8.3|
|(Xilinx Answer 60199)||UltraScale Devices - Hold violations seen on RX interface||v8.2||Work-around in answer record
|(Xilinx Answer 60198)||UltraScale Devices - RGMII - Timing not met on IO interface||v8.2||Work-around in answer record
|(Xilinx Answer 58041)||IPI board connection automation only supported with KC705 and AC701 boards||v8.0||Work-around in answer record|
|(Xilinx Answer 57377)||VHDL - update needed to provide unique file name if using multiple iterations of the core||v7.0||v7.0 (Rev 1)|
|(Xilinx Answer 57440)||MII - update to XDC constraints||v7.0||v7.0 (Rev 1)|
|(Xilinx Answer 56625)||Configuration Vector - Updates need to xdc file and Verilog bus2ip_addr bus||v7.0||v7.0 (Rev 1)|
|(Xilinx Answer 56267)||Undersized frames less than 14 bytes cause Example Design TX FIFO pointers misalignment||v4.5||v8.0|
|(Xilinx Answer 55356)||Full Duplex - Incorrect TX Statistics byte count seen for IFG Adjust less than 8||v5.5||v6.0|
|(Xilinx Answer 54785)||IFG Adjust values smaller than 9 not used when core is generated with half duplex support||v5.5||v6.0|