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AR# 54285

Soft Error Mitigation (SEM) v3.5 - Requirements for Support of Larger Densities of SPI Flash

Description

This answer record contains supplemental information to describe new parameters introduced to the SEM v3.5 (in ISE) example designs EXT shim to support larger densities of SPI Flash.

For the Vivado core, this information is in the SEM v4.0 Product Guide. For ISE, the information is provided in this answer record. Also, included at the bottom of the document is the list of SPI Flash devices which have been used in SEM hardware testing. For the Vivado core, this information is in the SEM v4.0 Product Guide in the Verification section.

Solution

The External Interface consists of four signals implementing a SPI bus protocol compatible, full duplex serial port. This interface is only present when one or both of the following controller options are enabled:

  • Error Correction by Replacement
  • Error Classification

The implementations of these functions require external storage. The system-level design example provides a fixed-function SPI bus master in the EXT shim to fetch data from a single external SPI Flash device.

The EXT shim uses the fast read command (0x0b) and can be configured to support one of several different families of SPI Flash. The family supported by default depends on the external storage size requirements. In the EXT shim system-level example design module, there are three parameters that control the command sequence sent to the SPI Flash device.

  • B_ISSUE_WREN
    • This indicates if a write enable command (0x06) must be issued prior to the issue of any other commands that modify the device behavior.
    • This must be set to 1 for N25Q devices, but generally set to 0 for other devices.
  • B_ISSUE_WVCR
    • This indicates if a write volatile configuration register command (0x81) must be issued to explicitly set the fast read dummy cycle count to eight cycles. The state machine in the EXT shim is byte-oriented and expects the fast read dummy cycle count to be eight. The volatile configuration register data is overwritten (0x8b).
    • This must be set to 1 for N25Q devices, but generally set to 0 for other devices.
  • B_ISSUE_EN4B
    • This indicates if an enable four-byte addressing command (0xb7) must be issued to explicitly enter the four-byte addressing mode.
    • This must be set to 1 for devices greater than 128 Mbit.

For storage requirements less than or equal to 128 Mbits, the EXT shim supports M25P devices by default (B_ISSUE_WREN = 0, B_ISSUE_WVCR = 0, B_ISSUE_EN4B = 0). These devices are not capable of four-byte addressing mode.

For storage requirements greater than 128 Mbits, the EXT shim supports higher-density N25Q devices by default (B_ISSUE_WREN = 1, B_ISSUE_WVCR = 1, B_ISSUE_EN4B = 1). These devices are capable of four-byte addressing mode.

Other supported devices include lower-density N25Q devices for storage requirements less than or equal to 128 Mbits (B_ISSUE_WREN = 1, B_ISSUE_WVCR = 1, B_ISSUE_EN4B = 0) and higher-density MX25 devices for storage requirements greater than 128 Mbits (B_ISSUE_WREN = 0, B_ISSUE_WVCR = 0, B_ISSUE_EN4B = 1).

The SPI Flash devices used in the SEM core hardware verification platform include:

  • M25P128 (ST Microelectronics / Numonyx)
  • M25L25635E (Macronix)
  • N25Q512 (Micron)
  • N25Q00 (Micron)
AR# 54285
Date Created 02/15/2013
Last Updated 04/03/2013
Status Active
Type General Article
Tools
  • ISE Design Suite - 14.5
IP
  • Soft Error Mitigation