I have created an IP core, using Manage IP or from a project IP catalog targeting a specific part. Then, when I read the IP core (read_ip) in Non-project mode Tcl script or Manage IP=>Open_Previously_Created_IP, the part for the IP core does not appear to be correct. The IP core targets are generated for the wrong part (e.g., xc7vx485tffg1157-1), instead of the device I selected.
Vivado issues messages similar to the following examples:
WARNING: [IP_Flow 19-1100] IP 'blk_mem_gen_v7_3_0' does not match the current project part 'xc7vx485tffg1157-1'. You can continue to use existing outputs but part differences may result in undefined behavior. Please review your project settings if this is unexpected."
An error will result if the IP in use does not support the xc7vx485tffg1157-1 device.
"Generating IP 'my_core' ...
Delivering 'Synthesis' files for IP 'My_core'.
Error: [Xilinx.com:ip:mig_7series:2.0-0] my_core: Target FPGA device"xc7k325t' provided by the mig project did not match with the selected FPGA device 'xc7vx485t' in the project settings. Please cross check the MIG project loader or review the project settings"
If the created IP core device is anything other than the default, there will be a device mismatch with generated warnings or errors.
The simple way to work around this issue is to run a set_property Tcl command before reading the IP cores. For example, the command "set_property part xc7k325tfbg900-2 [current_project]" is run before the read_ip commands.
In Vivado 2013.3, the IP association of IP core device and project device will be changed to require the user to issue a command to generate IP core targets in non-project mode. This will eliminate the issue described above and bring the IP related flows more in alignment with the general non-project mode use model which is intended to give the user more control of (and generally requires a user to control) the management of the files and operations.