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AR# 54357

Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - parallel_case, translate_off/translate_on, use_dsp48


This Answer record describes the Vivado Synthesis Attributes parallel_case, translate_off, translate_on, and use_dsp48, and also provides coding examples for them. 

The coding examples are attached to this answer record. The AR also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the Synthesis attributes covered in each example.


PARALLEL_CASE (Verilog Only)

Parallel case is valid only for Verilog designs. This attribute forces a case statement to be built as a parallel multiplexer. 

This also prevents the case statement from being transformed into a prioritized if-elsif cascade.

This attribute can only be controlled through the Verilog RTL.

Verilog Example

(* parallel_case *)
casex select
   4'b1xxx: res = data1;
   4'bx1xx: res = data2;
   4'bxx1x: res = data3;
   4'bxxx1: res = data4;

Known Issues:



TRANSLATE_OFF and TRANSLATE_ON instructs the Synthesis tool to ignore blocks of code. 

This can be useful to ignore source code that is not relevant for Synthesis, such as simulation code. 

These attributes are given within a comment in RTL code. The comment should start with one of the following keywords:

  • synthesis
  • synopsys
  • pragma

TRANSLATE_OFF starts the section of code to be ignored, and TRANSLATE_ON ends the section to be ignored. These attributes cannot be nested.

Be careful with the types of code that are included between the translate statements. 

If it is code that affects the behavior of the design, a simulator could use that code, and create a simulation mismatch.

Verilog Example

// synthesis translate_off

...Code to be ignored...

// synthesis translate_on

VHDL Example

-- synthesis translate_off

...Code to be ignored...

-- synthesis translate_on

Known Issues:



The use_dsp48 attributes allows a user to control how the Synthesis tool deals with arithmetic structures. 

By default, mults, mult-add, mult-sub, and mult-accumulate type structures go into DSP48 blocks. Adders, subtractors, and accumulators can also go into these blocks, but by default are implemented with the fabric instead of using DSP48 blocks. 

If this attribute is not specified, the default behavior is for Vivado Synthesis to determine the correct behavior. 

This attribute overrides the default behavior and forces these structures into DSP48 blocks, and is placed in the RTL on signals, architectures and components, entities and modules, with the following priority:

  1. Signals
  2. Architectures and components
  3. Modules and entities

Accepted values for this attribute are "yes" and "no."

Verilog Example

(* use_dsp48 = "yes" *) module test(clk, in1, in2, out1);

VHDL Example

attribute use_dsp48 : string;

attribute use_dsp48 of P_reg : signal is "no";

Known Issues:



Table 1: 

File Name Attribute Example
parallel_case.zip PARALLEL_CASE
translate_off_on.zip Translate Off/Translate On
use_dsp48.zip USE_DSP48


Associated Attachments

Name File Size File Type
translate_off_on.zip 1 KB ZIP
use_dsp48.zip 2 KB ZIP
parallel_case.zip 447 Bytes ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
55160 Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support N/A N/A
AR# 54357
Date Created 02/20/2013
Last Updated 06/04/2014
Status Active
Type Solution Center
  • Vivado Design Suite