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AR# 5437

VSS with M1.5: "Error: vhdlsim,19: Discrete range is not consistent with corresponding index subtype" in simprim_Vpackage.vhd

Description

Keywords: VSS, univhd, simprim_Vpackage, vhdlsim, SLV, STR

Urgency: Standard

General Description:

Running VSS using the vhdl libraries from Xilinx M1.5 I am getting the
following error:

**Error: vhdlsim,19:
Discrete range is not consistent with corresponding index subtype.

When I look at the function SLV_TO_STR in the simprim_Vpackage.vhd
file I see something similiar to the following which does not conform
to the definition of type string.


function SLV_TO_STR (
SLV : in std_logic_vector
) return string is

variable STR : string (SLV'high downto SLV'low);

begin
......
end SLV_TO_STR;

Solution

If the SLV, is a std_logic_vector (10 downto 0) the the STR, string
would also have to have a range (10 downto 0). This does not conform
to the definition of type string, since it is a positive array, with
a range from 1 to integer'high.

The fix which will be in the next release of the Xilinx software is
the following:

function SLV_TO_STR (
SLV : in std_logic_vector
) return string is

variable j : integer := SLV'length;
variable STR : string (SLV'length downto 1);


begin
for I in SLV'high downto SLV'low loop
case SLV(I) is
when '0' => STR(J) := '0';
when '1' => STR(J) := '1';
when 'X' => STR(J) := 'X';
when 'U' => STR(J) := 'U';
when others => STR(J) := 'X';
end case;
J := J - 1;
end loop;
return STR;
end SLV_TO_STR;

--------------------
This is fixed in 2.1i
AR# 5437
Date Created 01/19/1999
Last Updated 04/03/2000
Status Archive
Type General Article