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AR# 54384 MIG 7 Series DDR3 - changing DATA_PATTERN in sim_tb_top.v does not work as expected

Description


Version Found: v1.8
Version Resolved: See (Xilinx Answer 45195)

During MIG 7 series behavioral simulation, changing DATA_PATTERN from the default DEGEN_ALL to HAMMER in sim_tb_top.v does not show the correct hammer pattern of alternating ones and zeros. This is due to an issue in the mig_7series_v1_8_init_mem_pattern_ctr instance inside mig_7series_v1_8_traffic_gen_top.v in the rtl/traffic_gen folder which generates data patterns dependent on the DATA_MODE binary value instead of the DATA_PATTERN ASCII value.

Solution


The work-around is to change DATA_MODE inside mig_7serie s_v1_8_traffic_gen_top.v and DATA_PATTERN in sim_tb_top.v to the respective values listed below:

DATA_MODE Values

1: FIXED data mode. Data comes from the fixed_data_i input bus.
2: DGEN_ADDR (default). The address is used as the data pattern.
3: DGEN_HAMMER. All 1s are on the DQ pins during the rising edge of DQS, and all 0s are on the DQ pins during the falling edge of DQS.
4: DGEN_NEIGHBOR. All 1s are on the DQ pins during the rising edge of DQS except one pin. The address determines the exception pin location.
5: DGEN_WALKING1. Walking 1s are on the DQ pins. The starting position of 1 depends on the address value.
6: DGEN_WALKING0. Walking 0s are on the DQ pins. The starting position of 0 depends on the address value

Revision History
02/28/2013 - Initial release

Actions

AR# 54384
Date Created 02/28/2013
Last Updated 02/28/2013
Status Active
Type
Devices
  • Kintex-7
  • Artix-7
Tools
  • ISE Design Suite - 14.4
IP
  • MIG 7 Series
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