We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54384

MIG 7 Series DDR3 - changing DATA_PATTERN in sim_tb_top.v does not work as expected


Version Found: v1.8
Version Resolved: See (Xilinx Answer 45195)

During MIG 7 series behavioral simulation, I change DATA_PATTERN from the default DEGEN_ALL to HAMMER in the sim_tb_top.v file.

However it does not show the correct hammer pattern of alternating ones and zeros. 

This is due to an issue in the "mig_7series_v1_8_init_mem_pattern_ctr" instance inside "mig_7series_v1_8_traffic_gen_top.v" located in the rtl/traffic_gen folder. 

It generates data patterns dependent on the DATA_MODE binary value instead of the DATA_PATTERN ASCII value.


To work around this issue, change 

  1. DATA_MODE in mig_7series_v1_8_traffic_gen_top.v
  2. DATA_PATTERN in sim_tb_top.v

to the required value from the list below:


  • FIXED data mode. Data comes from the fixed_data_i input bus.
  • DGEN_ADDR (default). The address is used as the data pattern.
  • DGEN_HAMMER. All 1s are on the DQ pins during the rising edge of DQS, and all 0s are on the DQ pins during the falling edge of DQS.
  • DGEN_NEIGHBOR. All 1s are on the DQ pins during the rising edge of DQS except one pin. The address determines the exception pin location.
  • DGEN_WALKING1. Walking 1s are on the DQ pins. The starting position of 1 depends on the address value.
  • DGEN_WALKING0. Walking 0s are on the DQ pins. The starting position of 0 depends on the address value.

Revision History
02/28/2013 - Initial release

AR# 54384
Date Created 02/28/2013
Last Updated 08/14/2014
Status Active
Type Known Issues
  • Kintex-7
  • Artix-7
  • ISE Design Suite - 14.4
  • MIG 7 Series