Which addressing mode does Xilinx support for memory burst transactions, cacheline wrap or linear incrementing? What happens when an invalid mode is encountered?
Xilinx only supports the linear incrementing addressing mode (i.e., the two LSBs on the AD bus, AD[1:0] must be 00 during memory commands). In linear incrementing mode, the address is assumed to increment by one DWORD (4 bytes) for 32-bit transfers and by two DWORDS (8 bytes) for 64-bit transfers.
The PCI interface will issue a disconnect with data after the first data phase if anything other than the linear incrementing mode is encountered.