General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
Version Table This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version |
Vivado Tools Version |
|---|
| v7.0 |
2013.1 |
General Guidance The table below provides answer records for general guidance when using the LogiCORE IP CPRI core.
| Answer Record |
Title |
|---|
| NA |
NA |
Known and Resolved Issues The following table provides known issues for the LogiCORE IP CPRI core, starting with v7.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record |
Title |
Version Found |
Version Resolved |
|---|
| (Xilinx Answer 53561) |
Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon |
v6.1 |
v7.0 |
| (Xilinx Answer 53779) |
Design Advisory for Virtex-7 FPGA GTH Transceiver - RX Reset Sequence Requirement for Production Silicon |
v6.1 |
v7.0 |
| (Xilinx Answer 55009) |
Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase
Alignment in Buffer Bypass Mode |
v6.1 |
v7.0 |
Revision History
04/03/2013 - Initial release