We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54476

LogiCORE IP DUC/DDC Compiler - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the LogiCORE IP DUC/DDC Compiler core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP DUC/DDC Compiler core IP Page:


General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v3.0(Rev. 4) 2014.1
v3.0(Rev. 3) 2013.4
v3.0(Rev. 2) 2013.3
v3.0(Rev. 1) 2013.2
v3.0 2013.1

General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP DUC/DDC Compiler core.

Answer Record Title

Known and Resolved Issues

The following table provides known issues for the LogiCORE IP DUC/DDC Compiler core, starting with v3.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 59798) Behavioral simulation using Synopsys VCS simulator may give incorrect outputs v3.0(Rev. 4) N/A
(Xilinx Answer 58585) The core may issue a critical warning during implementation: "CRITICAL WARNING: [Netlist 29-98] The DSP48E2 multiplier has increased from 25x18 to 27x18" v3.0(Rev. 3) N/A
(Xilinx Answer 56376) Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation v3.0 N/A
(Xilinx Answer 55108) Vivado fails to upgrade DUC/DDC Compiler v2.0 from 14.2 PlanAhead to Vivado v2.0 v3.0

Revision History
03/17/2014 - Updated for 2014.1; added (Xilinx Answer 59798)
12/18/2013 - Updated for 2013.4; added (Xilinx Answer 58585)
06/26/2013 - Added (Xilinx Answer 56376)
04/03/2013 - Initial Release

Linked Answer Records

Child Answer Records

AR# 54476
Date Created 02/24/2013
Last Updated 11/10/2014
Status Active
Type Release Notes
  • Vivado Design Suite - 2013.1
  • DUC/DDC Compiler