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AR# 54518

LogiCORE IP Chroma Resampler - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP Chroma Resampler core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
For past known issue logs and ISE support information, see the IP Release Notes Guide (XTP025):
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

LogiCORE IP Chroma Resampler core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-chrom-resamp.html

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version
Core
Version
Vivado Tools
Version
v4.0 (Rev. 2) 2013.3
v4.0 (Rev. 1) 2013.2
v4.0 2013.1


Table 2 provides answer records for general guidance when using the LogiCORE IP Chroma Resampler core.

Table 2: General Guidance

Answer Record Title
N/A N/A


Known and Resolved Issues

The following table provides known issues for the LogiCORE IP Chroma Resampler core, starting with v4.0, initially released in Vivado 2013.1 design tools.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version
Found
Version
Resolved
(Xilinx Answer 57773) Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation? v3.01.a N/A
(Xilinx Answer 52215) Why does my core fail timing with a Critical Warning? v3.01.a v4.0 (Rev. 2)
(Xilinx Answer 56274) Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design? v4.0 v4.0 (Rev. 2)
(Xilinx Answer 55980) Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? v4.0 v4.0 (Rev. 1)


Revision History

10/23/2013 - Added v4.0 (Rev. 2) Version Table,(Xilinx Answer 57773) and updated Known and Resolved Issues table for 2013.3.
06/19/2013 - Added v4.0 (Rev. 1) to Version Table, (Xilinx Answer 56274), (Xilinx Answer 55980)
04/03/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44487 LogiCORE IP Chroma Resampler - Release Notes and Known Issues N/A N/A
61625 Video IP Example Design Landing Page N/A N/A
AR# 54518
Date Created 02/24/2013
Last Updated 11/10/2014
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
IP
  • Chroma Resampler