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AR# 54522

LogiCORE IP DisplayPort - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP DisplayPort core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.


Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP DisplayPort core IP Page:

http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-displayport.html

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core
Version
Vivado Tools
Version
v7.0 (Rev. 1)2016.2
v7.02016.1
v6.1 (Rev. 1)2015.4
v6.12015.3
v6.0 (Rev. 1)2015.2
v6.02015.1
v5.0 (Rev. 1)2014.4
v5.02014.3
v4.2 (Rev. 2)2014.2
v4.2 (Rev. 1)2014.1
v4.22013.4
v4.12013.3
v4.0 (Rev. 1)2013.2
v4.02013.1


General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP DisplayPort core.

Answer RecordTitle
(Xilinx Answer 63907)Does the DisplayPort IP support Fast AUX (FAUX) or Dual mode AUX?
(Xilinx Answer 65838)Can the UltraScale DisplayPort Sink support sources using Spread Spectrum Clocking (SSC) when receiving at 1.62 Gbps?
(Xilinx Answer 65837)What are the lnk_fwdclk_p/n clock signals that appear when targeting UltraScale devices, and how are they to be used?
(Xilinx Answer 65154)What is the HSYNC_WIDTH register and is there a related VSYNC_WIDTH register?
(Xilinx Answer 51560)How do I select the proper USER_PIXEL_WIDTH for my resolution?
(Xilinx Answer 64732)Does DisplayPort support adaptive sync or G-SYNC by NVidia?
(Xilinx Answer 64652)Does the DisplayPort core or reference designs support EDID or DisplayID?
(Xilinx Answer 61784)Why do I receive an error when trying to generate a bitstream that includes the DisplayPort core?
(Xilinx Answer 60227)What is the polarity of the User Data Interface Pins for the DisplayPort Source core?
(Xilinx Answer 59291)Does the DisplayPort Source DPCD Main Stream Attributes register have to match the timing of the video being input to the User Data interface?
(Xilinx Answer 42953)Design Advisory Master Answer Record for LogiCORE IP DisplayPort
(Xilinx Answer 34210)How do I connect the Display Port Core to my Display Port connector?
(Xilinx Answer 44843)Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?
(Xilinx Answer 46820)Does the Xilinx DisplayPort IP support eDP and features like Panel Self Refresh?
(Xilinx Answer 52299)Why is a -2 or -3 part required to support 5.4 Gb/s in 7 Series FPGAs?


Known and Resolved Issues

The following table provides known issues for the LogiCORE IP DisplayPort core, starting with v4.0, initially released in Vivado Design Suite 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

IP:

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 67433)Why does the DisplayPort Rx driver for the DisplayPort IP and DisplayPort subsystem sometimes fail to train when using the (DP159) production silicon?v7.0 (Rev. 1)
(Xilinx Answer 66371)When Enabling "Additional Transceiver Control and Status Ports", if I close the GUI and re-open it, this option is un-checked v6.1(Rev 1)v7.0
(Xilinx Answer 66372)Why does the option to select Quad Pixel remain disabled when changing the number of lanes from 1 back to 4? v6.1(Rev 1)v7.0
(Xilinx Answer 66373)Why does selecting YCrCb 422 in the GUI not have any effect in the Hardware?
v6.1(Rev 1)v7.0
(Xilinx Answer 65795)When should the SS Mode check box be selected?v6.0 (Rev. 1)v6.1
(Xilinx Answer 65133)Does XAPP1178 v2.0 run on the KC705 Rev 1.1 board?N/AN/A
(Xilinx Answer 63263)Why do 1 and 2 lane SST modes fail to link if the DisplayPort v5.0 is generated with MST enabled?v5.0v5.0 (Rev. 2)
(Xilinx Answer 62582)Why are the M_VID and M_AUD values double when the GT Interface Width is set to 32-bits?v5.0v5.0 (Rev.1)
(Xilinx Answer 61799)GTP and GTH - Production reset DRP sequence can hang, requiring a reconfiguration to recoverv4.2 (Rev. 1)v4.2 (Rev. 2)
(Xilinx Answer 38503)Why do I get an Critical Warning saying the Reed-Solomon Decoder license is not found, and an Error in Synthesis saying a license was not found when the DisplayPort core is configured as a DisplayPort Sink?v4.2N/A
(Xilinx Answer 61683)Why do I get an error Name Protected error when using Cadence IUS for simulation?v4.2 (Rev. 1)v4.2 (Rev. 2)
(Xilinx Answer 60627)Why can I not target the Automotive Aritx-7 (QArtix-7) devices?v4.2 (Rev. 1)N/A
(Xilinx Answer 59634)Why do I see a AUX channel timeout when performing larger AUX channel transactions?v4.0v4.2 (Rev. 1)
(Xilinx Answer 59288)Why does the PHY sometimes fail to return from reset when using the reset sequence in Figure 3-11 from the DisplayPort Product Guide PG064, December 18th, 2013?v4.2N/A
(Xilinx Answer 57951)Why do I get a Type mismatch error when simulating with Synopsys VCS H-2013.06-3?v4.1N/A
(Xilinx Answer 57836)Why is the Link Rate wrong when simulating with Cadence IUS 12.2-S016?v4.1N/A
(Xilinx Answer 57399)VESA Spec Termination Scheme Causes Corruption on the AUX State Machinev4.0v4.1
(Xilinx Answer 55359)Noise on the AUX Channel causes the Core AUX State Machine to Hangv4.0v4.1
(Xilinx Answer 56777)GTH Common Block Refclk is not Connected Causing DRC Errorv4.0v4.1
(Xilinx Answer 56681)Virtex-7 GTH - DisplayPort Core will not Synthesize Correctly in Non-Project Flowv4.0v4.1
(Xilinx Answer 56637)DisplayPort Sink Core Contains Incorrect Clocking Connection when selected for 5.4G Line Rate v4.0v4.1
(Xilinx Answer 56856)DisplayPort Core Does Not Link Train at 5.4G Line Ratev4.0v4.0
(Xilinx Answer 53538)Why does the DisplayPort Sink IIC Controller hold the SCL line in some cases when large amounts of noise are introduced into it via the AUX channel input? v3.2v4.0
(Xilinx Answer 53539)Why does the DisplayPort Source Stop sending audio after a reset?v3.2v4.0
(Xilinx Answer 56168)Error in Simulation - Test Failed when targeting Artix-7 FPGAsv3.2v4.0 (Rev 1)

Software Driver:

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 67274)Why does the CP_CURRENT (0x02) register value differ between the documentation and the driver?v2.0 (Rev. 1)N/A


Revision History:

07/14/2016Added v7.0 (Rev. 1) to Version Table, (Xilinx Answer 67274) and (Xilinx Answer 67433)
04/06/2016Added v7.0 to Version Table, (Xilinx Answer 63907)
11/24/2015Added v6.1 and v6.1 (Rev. 1) to Version Table, (Xilinx Answer 65795), (Xilinx Answer 65837), (Xilinx Answer 65838)
08/06/2015Added (Xilinx Answer 65154)
08/04/2015Added (Xilinx Answer 65133)
06/30/2015Added v6.0 (Rev. 1) to Version Table and (Xilinx Answer 64652), (Xilinx Answer 64732), (Xilinx Answer 51560)
04/01/2015Added v6.0 to Version Table
01/05/2015Added v5.0 (Rev. 1) to Version Table and (Xilinx Answer 63263)
10/22/2014Added (Xilinx Answer 62582)
10/08/2014Added v5.0 to Version Table
08/01/2014Added v4.2 (Rev. 2) to Version Table, (Xilinx Answer 61683), (Xilinx Answer 38503), (Xilinx Answer 61784), (Xilinx Answer 61799).
05/13/2014Added (Xilinx Answer 60627)
04/16/2014Added v4.2 (Rev. 1) to Version Table, (Xilinx Answer 59291), (Xilinx Answer 59288), (Xilinx Answer 59634), (Xilinx Answer 60227).
12/18/2013Added v4.2 to Version Table
10/23/2013Added v4.0 (Rev. 1) and v4.1 to Version Table, (Xilinx Answer 57836), (Xilinx Answer 57951) and updated Know and Resolved Issues table for 2013.3.
09/09/2013Added (Xilinx Answer 55359), (Xilinx Answer 57399)
07/23/2013Added (Xilinx Answer 56856)
07/17/2013Added (Xilinx Answer 56777)
07/03/2013Added (Xilinx Answer 56681)
06/28/2013Added (Xilinx Answer 56637)
05/29/2013Added (Xilinx Answer 56168)
04/03/2013Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
42953 Design Advisory Master Answer Record for LogiCORE IP DisplayPort N/A N/A
34210 LogiCORE IP Display Port - How do I connect the Display Port Core to my Display Port connector? N/A N/A
44843 LogiCORE IP DisplayPort v2.3 - Does the DisplayPort I2C over AUX support clock stretching for slower I2C slaves? N/A N/A
52299 LogiCORE IP DisplayPort v3.2 - Why is a -2 or -3 part required to support 5.4 Gb/s in 7 Series FPGAs? N/A N/A
46820 LogiCORE IP DisplayPort - Does the Xilinx DisplayPort IP support eDP and features like Panel Self Refresh? N/A N/A
53538 LogiCORE IP DisplayPort v3.2 - Why does the DisplayPort Sink IIC Controller hold the SCL line in some cases when large amounts of noise are introduced into it via the AUX channel input? N/A N/A
53539 LogiCORE IP DisplayPort v3.2 - Why does the DisplayPort Source core Stop sending audio after a reset? N/A N/A
56168 LogiCORE DisplayPort v3.2 - Error in Simulation - Test Failed when targeting Artix-7 N/A N/A
56681 LogiCORE IP DisplayPort v4.0, Virtex-7 GTH - DisplayPort core will not synthesize correctly in non-project flow N/A N/A
56777 LogiCORE IP DisplayPort v4.0 - GTH Common Block Refclk is not Connected Causing DRC Error N/A N/A
55359 LogiCORE DisplayPort v3.2 - Noise on the AUX Channel causes the Core AUX State Machine to Hang N/A N/A
57399 Spartan-6 - LogiCORE IP DisplayPort v3.2 - VESA Specification Termination Scheme Causes Corruption on the AUX State Machine N/A N/A
57836 LogiCORE IP DisplayPort v4.1 - Why is the Link Rate wrong when simulating with Cadence IUS 12.2-S016? N/A N/A
57842 LogiCORE Video PHY Controller - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
57951 LogiCORE DisplayPort v4.1 - Why does a type mismatch error occur when simulating with Synopsys VCS H-2013.06-3? N/A N/A
59288 LogiCORE DisplayPort v4.2 - Why does the PHY sometimes fail to return from reset when using the reset sequence in Figure 3-11? N/A N/A
59291 LogiCORE DisplayPort - Does the DisplayPort Source DPCD Main Stream Attributes register have to match the timing of the video being input to the User Data interface? N/A N/A
60227 LogiCORE IP DisplayPort - What is the polarity of the User Data Interface Pins for the DisplayPort Source core? N/A N/A
60627 LogiCORE DisplayPort - Why can I not target the Automotive Aritx-7 (XA Artix-7) devices? N/A N/A
59634 LogiCORE IP DisplayPort v4.0 - Why do I see a AUX channel timeout when performing larger AUX channel transactions? N/A N/A
57950 LogiCORE IP DisplayPort v3.2 - Support has been removed from ISE in 14.7 N/A N/A
61683 LogiCORE IP DisplayPort v4.2 (Rev.1) - Why do I receive a Name Protected error when using Cadence IUS for simulation? N/A N/A
38503 LogiCORE IP DisplayPort v4.2 - Why do I receive a Critical Warning saying the Reed-Solomon Decoder license is not found, and an Error in Synthesis saying a license was not found when the DisplayPort core is configured as a DisplayPort Sink? N/A N/A
61784 LogiCORE IP DisplayPort - Why do I recieve an error when trying to generate a bitstream that includes the DisplayPort core? N/A N/A
61799 LogiCORE DisplayPort v4.2 Rev. 1 and earlier - GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recover N/A N/A
62582 LogiCORE IP DisplayPort v5.0 - Why are the M_VID and M_AUD values doubled when the GT Interface Width is set to 32-bits? N/A N/A
63014 LogiCORE IP DisplayPort v5.0 - This answer record contains patch updates for the LogiCORE IP DisplayPort v5.0 N/A N/A
64652 LogiCORE IP DisplayPort - Do the DisplayPort core or reference designs support EDID or DisplayID? N/A N/A
64732 LogiCORE IP DisplayPort - Does DisplayPort support Adaptive-Sync or G-Sync by NVIDIA? N/A N/A
51560 LogiCORE DisplayPort - How do I select the proper USER_PIXEL_WIDTH for my resolution? N/A N/A
65133 LogiCORE DisplayPort - Does XAPP1178 v2.0 run on the KC705 Rev 1.1 board? N/A N/A
65154 LogiCORE IP DisplayPort - What is the HSYNC_WIDTH register and is there a related VSYNC_WIDTH register? N/A N/A
65795 LogiCORE IP DisplayPort v6.0 (Rev. 1) – When should the SS Mode check box be selected? N/A N/A
65838 LogiCORE DisplayPort v6.1 - Can the UltraScale DisplayPort Sink support sources using Spread Spectrum Clocking (SSC) when receiving at 1.62 Gbps? N/A N/A
66371 LogiCore DisplayPort v6.1 (Rev. 1) - When Enabling "Additional Transceiver Control and Status Ports", if I close the GUI and re-open it, this option is un-checked N/A N/A
66372 LogiCore DisplayPort v6.1 (Rev. 1) - Why does the option to select Quad Pixel remain disabled when changing the number of lanes from 1 back to 4? N/A N/A
66373 LogiCore DisplayPort v6.1 (Rev. 1) - Why does selecting YCrCb 422 in the GUI not have any effect in the Hardware? N/A N/A
66301 LogiCORE DisplayPort v6.1 (Rev. 1) - Patch Updates for the DisplayPort IP N/A N/A
66565 LogiCORE DisplayPort v6.1 (Rev. 1) - Why is the lnk_fwdclk_p/n reference input clock grounded for the RX IP for UltraScale Devices? N/A N/A
63907 LogiCORE IP DisplayPort - Does the DisplayPort IP support Fast AUX (FAUX) or Dual mode AUX? N/A N/A
66907 LogiCORE DisplayPort v6.1 (Rev. 1) - Why do I see training Lost interrupts after training is done and while the Video is Running in the RX core? N/A N/A
67274 LogiCORE DisplayPort Receiver v7.0 (Rev. 1) - Why does the CP_CURRENT (0x02) register value differ between the documentation and the driver? N/A N/A

Associated Answer Records

AR# 54522
Date Created 02/24/2013
Last Updated 07/18/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3
IP
  • DisplayPort