This answer record contains the Release Notes and Known Issues for the LogiCORE IP Image Statistics Engine core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP Image Statistics Engine core IP Page:
Note: Not recommended for new designs. The core is removed from IP catalog as of 2014.1. Please contact Xylon, our IP partner, for solutions related to image statistics.
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|v6.0 (Rev. 2)||2013.3|
|v6.0 (Rev. 1)||2013.2|
The table below provides answer records for general guidance when using the LogiCORE IP Image Statistics Engine core.
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Image Statistics Engine core, starting with v6.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 60219)||LogiCORE IP Image Statistics v5.01a, v6.0 - Why is the Image Statistics core histogram output less than the total number of pixels in the image?||v5.01.a||v6.0 (Rev. 1)|
|(Xilinx Answer 58551)||Why do the YCrCb histogram results appear to be in the wrong bin location?||v5.01.a||N/A|
|(Xilinx Answer 52215)||Why does my core fail timing with a Critical Warning?||v5.01.a||v6.0 (Rev. 2)|
|(Xilinx Answer 56274)||Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?||v6.0||v6.0 (Rev. 2)|
|(Xilinx Answer 55980)||Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?||v6.0||v6.0 (Rev. 1)|