This answer record contains the Release Notes and Known Issues for the LogiCORE IP SMPTE2022-5/6 Video Over IP Receiver core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP SMPTE2022-5/6 Video Over IP Receiver core IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|v5.0 (Rev. 5)||2016.2|
|v5.0 (Rev. 4)||2016.1|
|v5.0 (Rev. 3)||2015.4|
|v5.0 (Rev. 2)||2015.3|
|v5.0 (Rev. 1)||2015.2|
|v3.0 (Rev. 4)||2014.1|
|v3.0 (Rev. 3)||2013.4|
|v3.0 (Rev. 2)||2013.3|
|v3.0 (Rev. 1)||2013.2|
The table below provides answer records for general guidance when using the LogiCORE IP SMPTE2022-5/6 Video Over IP Receiver core.
|(Xilinx Answer 67368)||XAPP1259/XAPP1199 - What process should I use to change the Match Header on the RX?|
|(Xilinx Answer 64824)||How do I calculate the Out Of Range (OOR) buffer threshold?|
|(Xilinx Answer 63118)||How can I adjust the FEC processing delay to compensate for delayed UDP or RTP packets that might cause FEC recovery to fail?|
|(Xilinx Answer 63109)||Can I update the channel configuration registers when the channel is enabled?|
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP SMPTE2022-5/6 Video Over IP Receiver core, starting with v3.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 65330)||Why does the video output stop after a few frames, when the core is generated without the Forward Error Correction (FEC) Engine included?||v5.0||v5.0 (Rev. 2)|
|(Xilinx Answer 64202)||Why do I see the Network Differential register value jump around when sending 1080i SDI with no impairments, and both FEC and Seamless enabled?||v4.0||v5.0|
|(Xilinx Answer 63846)||Why does setting the HD-SDI FEC (4x750) with a controlled burst cause missing packets?||v4.0||v5.0|
|(Xilinx Answer 62794)||Why do I get Duplicate Packets, Missing Packets, and Out of Range Packet errors when receiving non-UDP packets?||v4.0||v4.0 (Rev. 2)|
|07/07/2016||Added v5.0 (Rev. 5) to Version Table and (Xilinx Answer 67368)|
|04/22/2016||Added v5.0 (Rev. 3), v5.0 (Rev. 4) to Version Table|
|09/30/2015||Added v5.0 (Rev. 1), v5.0 (Rev. 2) to Version Table and (Xilinx Answer 65330)|
|06/19/2015||Added (Xilinx Answer 64824)|
|04/01/2015||Added v5.0 to Version Table, (Xilinx Answer 64202) and (Xilinx Answer 63846)|
|12/12/2014||Added (Xilinx Answer 63109), (Xilinx Answer 63118)|
|11/19/2014||Added v4.0 (Rev. 1) to Version Table and (Xilinx Answer 62794)|
|10/08/2014||Added v3.0 (Rev. 3), v3.0 (Rev. 4) and v4.0 to Version Table|
|10/23/2013||Added v3.0 (Rev. 1) and v3.0 (Rev. 2) to Version Table|