This answer record contains the Release Notes and Known Issues for the MIPI D-PHY Controller Core and includes the following:
LogiCORE MIPI D-PHY Controller Core IP Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version||IP Patches|
|v3.1 (Rev.1)||2017.2||(Xilinx Answer 69760)|
|v3.1||2017.1||(Xilinx Answer 69273)|
|v3.0 (Rev. 1)||2016.4||(Xilinx Answer 68810)|
|v2.0 (Rev. 1)||2016.2|
The table below provides Answer Records for general guidance when using the LogiCORE MIPI D-PHY Controller core.
|Article Number||Article Title|
|(Xilinx Answer 67249)||What is the maximum value of start-up time before High-speed data transfer?|
|(Xilinx Answer 66088)||Are there plans to support MIPI D-PHY v1.2?|
Known and Resolved Issues
The following table provides known issues for the MIPI D-PHY Controller core, starting with v1.0, initially released in Vivado 2015.3.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Article Number||Article Title||Version Found||Version Resolved|
|(Xilinx Answer 69671)||When using 7 Series Devices to implement MIPI D-PHY TX, why do we see overshoot on the output signal during HS-->LP transmission?||v3.1 (Rev. 1)||v4.0|
|(Xilinx Answer 69931)||When using MIPI D-PHY TX, why is the HS-PREPARE length violating MIPI D-PHY specification version 1.1?||v3.1 (Rev. 1)||N/A|
|(Xilinx Answer 69766)||When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes when targeting 7 Series devices?||v3.1 (Rev. 1)||N/A|
|(Xilinx Answer 67365)||What is the behavior of receiver IP on SoT pattern and why do I not see an error when sending "BC" and receiving "B8"?||v2.0||v3.0|
|(Xilinx Answer 69274)||Why does the ulpsactivenot only asserted for one clock period for the MIPI D-PHY Controller RX?||v3.1||N/A|
|(Xilinx Answer 69057)||Why is an SOTsynchs error generated from MIPI DPHY RX IP or MIPI CSI-2 RX Subsystem?||v3.0 (Rev. )||v3.1|
|(Xilinx Answer 68603)||Slave Mode (Shared logic in example design) D-PHY RX IP does not work when it is sharing resources with Master mode (Shared Logic in core) D-PHY RX IP||v3.0 (Rev .1)||v3.1|
|(Xilinx Answer 68603)||Why does the Slave IP not work after updating to 2016.4?||v3.0 (Rev. 1)3.0 (Rev. 1)||N/A|
|(Xilinx Answer 67296)||Are multi-lane use cases supported in MIPI D-PHY IP?||v2.0||N/A|
|(Xilinx Answer 67258)||Why is there a change to the rxvalidhs behavior when receiving in high-speed mode?||v1.01.0||v2.0|
|11/03/2017||Added (Xilinx Answer 69766) (Xilinx Answer 69671) (Xilinx Answer 69931) and (Xilinx Answer 69760)|
|10/23/2017||Added v3.1 (Rev.1) and v4.0 to Version Table and (Xilinx Answer 67365)|
|06/05/2017||Added (Xilinx Answer 69274)|
|04/05/2017||Added v3.1 to Version Table, (Xilinx Answer 68803), (Xilinx Answer 68810) and (Xilinx Answer 69057)|
|02/07/2017||Added v2.0 (Rev.1), v3.0 and v3.0 (Rev.1) to Version Table and (Xilinx Answer 68603)|
|05/31/2016||Added (Xilinx Answer 67258), (Xilinx Answer 67296) and (Xilinx Answer 67249)|
|04/06/2016||Added v2.0 to Version Table|
|12/07/2015||Added (Xilinx Answer 66088)|