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AR# 54606

Release Notes and Known Issues for Vivado Logic Debug Core in Vivado

Description

This answer record contains the Release Notes and Known Issues for the Vivado Logic Debug Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Vivado Logic Debug Core Documentation and Videos:

LogiCORE Integrated Logic Analyzer (ILA) Core IP Page:

http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ila.html

Solution

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Known and Resolved Issues

The following table provides known issues for Vivado Logic Debug and Vivado VIO, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version
Found
Version
Resolved
(Xilinx Answer 62634) 2014.3 -IBERT - Vivado Hardware Manager the contour plot is not being generated 2014.3
(Xilinx Answer 62636) 2014.3 IBERT 2D eyescan java.lang.NegativeArraySizeException
2014.3
(Xilinx Answer 62049) 2014.2 - Vivado Logic Debug - ERROR: [Place 30-188] UnBuffered IOs 2014.2 2014.3
(Xilinx Answer 61900) 2014.2 - Removing the debug core from the synthesized design, xdc constraints still there 2014.2 na
(Xilinx Answer 60856) 2014.2 - ERROR: [ChipScope 16-119] Implementing debug core dbg_hub failed. 2014.2 na
(Xilinx Answer 60631) 2014.1 Error triggering ILA with option "Window data depth = 1" and "Number of windows = 2" 2014.1 2014.2
(Xilinx Answer 60086) 2014.1 - [16-215] This design contains the following cells that cannot be upgraded 2014.1 2014.2
(Xilinx Answer 60049) 2014.1 - Vivado Critical Warning [Timing 38-249] in ChipScope design imported from ISE 2014.1 na
(Xilinx Answer 59457) 2013.4 Failed to get a response from the Debug Core Hub 2013.4 2014.1
(Xilinx Answer 58565) 2013.4 Timing Error in Coregen ChipScope Core When Opened in Vivado 2013.4 na
(Xilinx Answer 59280) 2013.4 - Logic Debug - Cannot Create Netlists for an ILA 2013.4 2014.1
(Xilinx Answer 58104) 2013.x Vivado Hardware Tools - Hardware Session Dependencies 2013.4 2014.1
(Xilinx Answer 58349) 2013.3 Vivado 2013.3 - ILA - Failed to Generate Debug IP 2013.3 2013.4
(Xilinx Answer 58103) 2013.3 Vivado Hardware Tools - Clock Selection Enhancement 2013.3 2014.2
(Xilinx Answer 57665) 2013.3 Vivado IP_ILA - ILA is generating a TRIG OUT when it receives an external TRIG IN 2013.3 2014.1
(Xilinx Answer 57648) 2013.3 Vivado IP_ILA - The ILA core captures incorrect data if the trigger position is set to 0 2013.3 2013.4
(Xilinx Answer 57682) 2013.3 Vivado IP-ILA - The ILA Probe_Ports(0....7) tab turns red if the 1024 Probe 2013.3 2013.4
(Xilinx Answer 56431) Vivado Logic Debug - mark_debug attribute not applied to ILA and VIO if language is VHDL 2013.2 2013.3
(Xilinx Answer 56430) Vivado Logic Debug - ILA GUI allows sample depths beyond available BRAM 2013.2 2013.3
(Xilinx Answer 56429) Vivado Logic Debug - Static nets connected to debug cores (ILA/VIO) are not preserved 2013.2 2014.1
(Xilinx Answer 56428) Vivado Logic Debug - Date stamps of ILA waveforms are incorrect when opening a .zip file 2013.2 2013.3
(Xilinx Answer 56427) Vivado Logic Debug - 2013.1 - create_debug_port documentation out of date and incorrect 2013.2 2013.3
(Xilinx Answer 56426) Vivado Logic Debug - IP properties get swapped when importing into new project 2013.2 2013.3
(Xilinx Answer 56425) Vivado Logic Debug - ILA 2.1 and VIO 2.0 cores optimized out by Synplify 2013.2 2013.3
(Xilinx Answer 53960) EDK + ChipScope is Cross Triggering enabled on Zynq, how to do it? 2013.1 na
(Xilinx Answer 54592) Vivado - CSE Server - Can't run vcse_server with UNC path 2013.1 na
(Xilinx Answer 54817) Debug IP from 2012.X does not appear in 2013.1 2012.4 2013.1
(Xilinx Answer 54406) Vivado Logic Debug - Data vs. Data Plotter 2012.4 na
(Xilinx Answer 52939) Vivado - Lab Tools - ERROR: [Labtools 27-147] and ERROR: [Labtools 27-146] 2012.4 2013.1



AR# 54606
Date Created 02/27/2013
Last Updated 04/06/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
IP
  • Debug and Verification