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AR# 54607

Release Notes and Known Issues for Serial I/O Debug in Vivado

Description

This answer record contains the Release Notes and Known Issues for the Serial I/O Debug Cores and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

This answer record covers all Vivado Serial I/O Debug Cores; this includes GTP, GTH, GTX, and GTX.

LogiCORE ChipScope Pro IBERT for 7 Series GTP Core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/chipscope_ibert_7series_gtp.html

LogiCORE ChipScope Pro IBERT for 7 Series GTH Core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/chipscope_ibert_7series_gth.html

LogiCORE ChipScope Pro IBERT for 7 Series GTX Core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/chipscope_ibert_7series_gtx.html

LogiCORE ChipScope Pro IBERT for 7 Series GTZ Core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ibert_7series_gtz.html

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in the Vivado tool.

Known and Resolved Issues

The following table provides known issues for the Vivado Serial IO Debug initially released in Vivado Design Suite 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 62027) 2014.2 - IBERT VC7222 IBERT design fails with no link status 
2014.2 2014.3
(Xilinx Answer 60201) 2014.1 - IBERT_Ultrascale_GTH IP support for '-1L' devices  2014.1 TBA
(Xilinx Answer 60030) 2014.1 - IBERT - DRC violation Error: [Drc 23-20] during bitstream generation  2014.1 2014.2
(Xilinx Answer 60029) 2014.1 - IBERT - Design fails with error [Place 30-642] Placement Validity Check 2014.1 2014.2
(Xilinx Answer 56417) Vivado Serial I/O Debug - Hardware Tree shows old status when Link View Status changes 2013.2 2013.3
(Xilinx Answer 56416) Vivado Serial I/O Debug - "Don't show this dialog again" box does not function correctly 2013.2 2013.3
(Xilinx Answer 56414) Vivado Serial I/O Debug - Link view does not auto-refresh with 7 Series 580T GTZ 2013.2 2013.3
(Xilinx Answer 56413) Vivado Serial I/O Debug - Eyescan filled contour plot has antennas in Virtex-7 2013.2 2013.3
(Xilinx Answer 55292) 2013.1 - Vivado Serial Analyzer - "set_property" commands each require a "commit" when writing commands to the Tcl console 2013.1 2013.2
(Xilinx Answer 54023) Artix-7 - IBERT - Generating an IBERT core for Artix-7 devices 2012.4 2013.1
(Xilinx Answer 54104) 2012.4 IBERT - "ERROR: [Common 17-11] Failed to parse xmsgs file xst.xmsgs - Invalid XML token 2012.4 na
(Xilinx Answer 54332) Virtex-7, Vivado SIOD - GTH 2.01 fails timing using the example design 2012.4 2013.1
(Xilinx Answer 53166) 2012.4 - Virtex-7 GTH IBERT does not enable DFE by default 2012.4 2013.1
(Xilinx Answer 53721) 2012.4 - IBERT - IBERT 7 series GTZ flow script and instructions 2012.4 na


Revision History


04/30/2014-  Updated for 2014.1
10/23/2013 - Updated for 2013.3
06/14/2013 - Updated for 2013.2
04/03/2013 - Initial release (2013.1)

AR# 54607
Date Created 02/27/2013
Last Updated 11/10/2014
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2