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AR# 54643 IP Release Notes and Known Issues for 7 Series Integrated Block for PCI Express for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the 7 Series Integrated Block for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Xilinx PCI Express Cores Page:
http://www.xilinx.com/technology/protocols/pciexpress.htm

Solution

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Changes in v2.0

  • Lower case ports for Verilog
  • Added Zynq Support
  • Fixed Reset Sequence issue with GTPs
  • Fixed TXOUTCLK flatline issue
  • Fixed the issue with GUI to select the optional frequency for g2x4, 128-bit configuration. Now the selection for 250Mhz optional frequency is removed as it is not supported configuration
  • Fixed XSIM issues with VHDL version of the core
  • Changed upper case portlevel signals to lower case (clocking interface for partial re-configuration and ICAP interface)
  • Added pipe_mmcm_rst_n signal at the port level as input in the core top file.
  • All Kintex devices, Virtex 2000T, Artix 100t/ffg676, 200T/fbg676,ffg1156 are marked as Production. Option is added in GUI to select GES_and_Production
  • Tandem Configuration - The option is enabled independent of the Dev board selection for Kintex 325/ffg900 and Virtex 485/ffg1761/PCIe Block X1Y0
  • Tandem Confguration - Create Bin files for stage 2, Back Up & restore of bitstream generation settings

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v2.0 2013.1
v1.8 2012.4


Known and Resolved Issues

The following table provides known issues for the 7 Series Integrated Block for PCI Express core, starting with v2.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Article Number Article Title Version Found Version Resolved
(Xilinx Answer 55311) Downstream Memory Write transactions fail in VHDL example design simulation for the core generated with 128 bit interface width
v2.0
 Not Resolved Yet
(Xilinx Answer 53250) Setup timing violation on userclk1 v1.8 Not Resolved Yet
(Xilinx Answer 50683) MSI Per Vector Masking Capability Support v1.7 Not Resolved Yet
(Xilinx Answer 50692) The core may truncate some DLLPs/TLPs during the process of going into Recovery v1.4 Not Resolved Yet
(Xilinx Answer 50835) VHDL Simulation support for Root Port Configuration v1.6 Not Resolved Yet
(Xilinx Answer 47626) VHDL Simulation Support in Endpoint Configuration v1.4 v2.0 (Use XSIM)
(Xilinx Answer 47628) Timing Violations in Certain IP Configurations v1.4 Not Resolved Yet


Revision History
04/03/2013 - Initial release

Actions

AR# 54643
Date Created 04/03/2013
Last Updated 04/03/2013
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
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