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AR# 54645 IP Release Notes and Known Issues for Virtex-7 FPGA Gen3 Integrated Block for PCI Express for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Xilinx PCI Express Cores Page:
http://www.xilinx.com/technology/protocols/pciexpress.htm

Solution

General Information

  • For release notes on v1.5 of the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core, see (Xilinx Answer 47441).

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Changes in v2.0

  • Lower case ports for Verilog
  • Removed DRP Ports from user interface
  • pipe_mmcm_rst_n has been provided to user interface
  • Added Production option for all the devices
  • Added Root Port Configuration Support
  • Added ASPM support
  • Enabled the Tandem configuration option for 690T-FFG1761 and PCIe Block X0Y1 irrespective of the development board selection

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v2.0 2013.1
v1.4 2012.4


Known and Resolved Issues

The following table provides known issues for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core, starting with v2.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 54902) IES/GES Device Support in Vivado 2013.1 and ISE Design Suite 14.5 v2.0 Not Resolved Yet
(Xilinx Answer 55309) ERROR:Place:1340 - PAD.pci_exp_rxn<1> is tied to GTHE_CHANNEL.pcie3_7x_v1_4_i/inst/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1]   
v2.0
 Not Resolved Yet
(Xilinx Answer 53151) Rate change back to Gen3 speed fails on x79 motherboard v1.3 Not Resolved Yet
(Xilinx Answer 52503) How to access the core via DRP ports? v1.3 Not Resolved Yet
(Xilinx Answer 50837) Some features in Endpoint Configuration not verified v1.2 Not Resolved Yet
(Xilinx Answer 47604) Incorrect Byte Count set when responding to Poisoned AtomicOp Request v1.1 Not Resolved Yet
(Xilinx Answer 47615) Timing Violations observed in certain IP configurations v1.1 Not Resolved Yet


Revision History
04/03/2013 - Initial release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
54902 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - IES/GES Device Support in Vivado 2013.1 and ISE Design Suite 14.5 N/A N/A

Actions

AR# 54645
Date Created 04/03/2013
Last Updated 04/03/2013
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
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