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AR# 54646

AXI Bridge for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the AXI Bridge for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


General Information

For AXI Bridge for PCI Express v1.09.a core release notes, see (Xilinx Answer 44969).

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v2.8 (Rev2)2016.3
v2.8 (Rev1)2016.2
v2.6 (Rev1)2015.2
v2.5 (Rev2)2014.4
v2.5 (Rev1)
v2.3 (Rev1)2014.1

Changes in v2.8 (Rev2)

  • ¬†Feature Enhancement
    • Source HDL files are concatenated into a single file to speed up synthesis and simulation; no changes required by the user
    • Added DRC for AXIS_CTL_SIZE for RP and EP
    • Updated Tooltip for BASEADDR and HIGHADDR parameters in core configuration GUI page
    • Changed default value for HIGHADDR to 0x00001FFF
    • Added Tie off for M_AXI interface.
  • Other
    • Revision change in one or more subcores

Design Advisories

(Xilinx Answer 62296)Design Advisory for 7 Series/Virtex-7 FGPA Gen3 Integrated Block for PCI Express / AXI Bridge for PCI Express (Vivado 2014.1/2014.2/2014.3) - Tool reports 'constant_clock' and 'unconstrained_internal_endpoints' when implementing core configured as Gen1
(Xilinx Answer 62770) Design Advisory for 7 Series Integrated Block for PCI Express / AXI Bridge for PCI Express (Vivado 2013.3 - Vivado 2014.3) - Link training issue with GTP devices

Tactical Patch

The following table provides a list of tactical patches for the AXI Bridge for PCI Express core applicable on corresponding Vivado tool versions.

Answer Record Core Version (After installing the Patch)Tool Version
(Xilinx Answer 63472)
v2.5 (Rev. 3)
(Xilinx Answer 63229) v2.5 (Rev. 2)2014.4
(Xilinx Answer 63182)v2.6 (Rev. 2)2015.2
(Xilinx Answer 65645)
v2.6 (Rev. 3)
(Xilinx Answer 65647)
v2.7 (Rev. 65647)
(Xilinx Answer 66348)v 2.7 (Rev. 66348)2015.4

Known and Resolved Issues

The following table provides known issues for the AXI Bridge for PCI Express core, starting with v2.0, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 66348)AXI Interface clock frequency too slow for x2Gen2 configuration in Zynq -1 devicesv2.7 (Rev1)v 2.7 (Rev. 66348)
(Xilinx Answer 65647)Erroneous result when the core receives MSI packet when other traffic is in progress (Vivado 2015.3)v2.7v2.7 (Rev1)
(Xilinx Answer 65645)Erroneous result when the core receives MSI packet when other traffic is in progress (Vivado 2015.2)
v2.6 (Rev1)v2.7 (Rev1)
(Xilinx Answer 65588)Timing issue with post-Synthesis DCP implementationv2.5(Rev2)Not Resolved Yet
(Xilinx Answer 62854)Excessive BUFG usage v2.5v2.5(Rev1)
(Xilinx Answer 62265) Incorrect default clock placement for KC705 Boardv2.5v2.5 (Rev2)
(Xilinx Answer 60440)Core incorrectly decodes AXI BAR addresses v2.3(Rev1)v2.4
(Xilinx Answer 61491)Example design simulation of the core configured for link width greater than x1 always trains down to x1 in some configurationsv2.4v2.5
(Xilinx Answer 61248)
Incorrect Generation of x8 link width core at Gen2 Speed v2.3(Rev1)v2.5
(Xilinx Answer 55711)Timing Issue in the Corev2.3Not Resolved Yet
(Xilinx Answer 59900)Post Synthesis/Implementation Netlist Functional/Timing Simulation Support v2.3 (Rev1)Not Resolved Yet
(Xilinx Answer 58738)
Zynq 7015 (clg485 package) / Artix 35t (cpg236 and csg325 packages) and 50t devices support v2.3v2.3(Rev1)
(Xilinx Answer 57835)Root Port Receives Slave Error During Enumeration Causing Processor to Hang v1.08.av2.2
(Xilinx Answer 56647)Core Constraints are not Generatedv2.1v2.2
(Xilinx Answer 55348)Interrupt Decode Register gets wrongly set when performing DMA with ASPM enabled in RC modev2.0Not Resolved Yet
(Xilinx Answer 55349)AXI Bridge becomes unresponsive when performing DMA with ASPM enabled in RC modev1.06.aNot Resolved Yet
(Xilinx Answer 55350)The core in EP mode fails with corrupted data written to memory when configured for x4Gen2 on Zynq devicesv1.06.av2.0
(Xilinx Answer 55351)Missing completion for Memory Read when configured as RC x4Gen2 on Zynq devicesv1.06.a v2.0

Other Information

(Xilinx Answer 60372) What is the frequency of the axi_aclk_out clock in Gen1x1 configuration?
(Xilinx Answer 53377) AXI Bridge for PCI Express - How do I configure the core with non-prefetchable 64-bit BAR?
(Xilinx Answer 60372) AXI Bridge for PCI Express v2.3 - What is the frequency of axi_aclk_out clock in Gen1x1 configuration?
(Xilinx Answer 65062) AXI Memory Mapped for PCI Express Address Mapping

Revision History

04/03/2013Initial release
06/19/2013Updated for 2013.2 Release
08/24/2013Added (Xilinx Answer 56652)
08/26/2013Added (Xilinx Answer 56647)
10/07/2013Added (Xilinx Answer 57835)
10/23/2013Updated for 2013.3 Release
12/18/2013Updated for 2013.4 Release
01/14/2014Added (Xilinx Answer 59083) and (Xilinx Answer 59084)
02/28/2014Added (Xilinx Answer 58738)
04/16/2014Updated for 2014.1 Release
04/28/2014Added (Xilinx Answer 60372)
06/04/2014Updated for 2014.2 Release
06/24/2014Added (Xilinx Answer 61248)
07/15/2014Added (Xilinx Answer 61491)
07/08/2014Added (Xilinx Answer 60440)
10/08/2014Updated for 2014.3 Release
11/09/2014Added (Xilinx Answer 62296)
11/24/2014Updated for 2014.4 Release
01/09/2015Added Tactical Patch Section
02/05/2014Added (Xilinx Answer 63472)
04/15/2015Updated for 2015.1 Release
06/24/2015Updated for 2015.2 Release
07/21/2015Added (Xilinx Answer 63182)
10/30/2015Updated for 2015.3 Release
11/24/2015Updated for 2015.4 Release
01/14/2016Added (Xilinx Answer 66348)
04/13/2016Updated for 2016.1 Release
08/06/2016Updated for 2016.2 Release
10/05/2016Updated for 2016.3 Release

Linked Answer Records

Child Answer Records

AR# 54646
Date Created 02/28/2013
Last Updated 10/13/2016
Status Active
Type Release Notes
  • AXI PCI Express (PCIe)