This answer record contains the Release Notes and Known Issues for the AXI Bridge for PCI Express Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Xilinx PCI Express Cores Page:
http://www.xilinx.com/technology/protocols/pciexpress.htm
General Information
For AXI Bridge for PCI Express v1.7 core release notes, see (Xilinx Answer 44969).
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Version Table
This table correlates the core version to the Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v2.0 | 2013.1 |
Changes in v2.0
Known and Resolved Issues
The following table provides known issues for the AXI Bridge for PCI Express core, starting with v2.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 55348) | Interrupt Decode Register gets wrongly set when performing DMA with ASPM enabled in RC mode | v2.0 | Not Resolved Yet |
| (Xilinx Answer 55349) | AXI Bridge becomes unresponsive when performing DMA with ASPM enabled in RC mode | v1.06.a | Not Resolved Yet |
| (Xilinx Answer 55350) | The core in EP mode fails with corrupted data written to memory when configured for x4Gen2 on Zynq devices | v1.06.a | v2.0 |
| (Xilinx Answer 55351) | Missing completion for Memory Read when configured as RC x4Gen2 on Zynq devices | v1.06.a | v2.0 |
Revision History
04/03/2013 - Initial release