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AR# 54648 IP Release Notes and Known Issues for LogiCORE IP Serial RapidIO Gen2 Core for Vivado 2013.1 and Forward

This answer record contains the Release Notes and Known Issues for the LogiCORE IP Serial RapidIO Gen2 Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Xilinx PCI Express Cores Page:
http://www.xilinx.com/technology/protocols/pciexpress.htm

General Information 

For LogiCORE IP Serial RapidIO Gen2 v1.7 release notes, see (Xilinx Answer 55339).

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table 

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v2.0 2013.1
v1.6 2012.4

 

Changes in v2.0

  • Added support for Zynq
  • Updated Artix-7 GT Wrappers
  • Added QPLL and CPLL clock resets to GTX wrappers

Known and Resolved Issues 

The following table provides known issues for the LogiCORE IP Serial RapidIO Gen2 core, starting with v2.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Article Number Article Title Version Found Version Resolved
 (Xilinx Answer 53937)  phy_link_reset doesn't work
 v1.6
v2.0
(Xilinx Answer 55340) Occassional PNAs seen for x1 configurations running with IDLE2 v1.6 v2.0
(Xilinx Answer 53542) Link might train down on 6.25Gbaud x2 and 6.25Gbaud x4 core configurations v1.6 Not Resolved Yet
(Xilinx Answer 55341) The tool generates the same GT Wrapper XCO file for both Kintex-7 and Virtex-7 Devices v1.6 Not Resolved Yet
(Xilinx Answer 54372) Support for devices with GTH v1.6 Not Resolved Yet
(Xilinx Answer 55153) Artix-7 core behavioral simulation fails with "ERROR: TEST FAILED" message v2.0 Not Resolved Yet
(Xilinx Answer 55154) Design might not meet timing for certain configurations of the core v2.0 Not Resolved Yet


Other Known Issues:

  • PlanAhead tool is not supported flow.  All development should be done through the Vivado tool.

Revision History:
04/03/2013 - Initial Release

AR# 54648
Date Created 04/05/2013
Last Updated 04/05/2013
Status Active
Type Release Notes
IP
  • Serial RapidIO
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