UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54648

LogiCORE IP Serial RapidIO Gen2 Core - Release Notes and Known Issues for Vivado 2013.1 and newer tools

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP Serial RapidIO Gen2 Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward. 


Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Solution

General Information

For LogiCORE IP Serial RapidIO Gen2 v1.7 release notes, see (Xilinx Answer 55339).

SRIO Gen2 v2.0 Rev1 Patch is available in (Xilinx Answer 55737).

SRIO Gen2 v2.0 Rev2 Patch is available in (Xilinx Answer 56660).

SRIO Gen2 v3.1 Rev2 Patch is available in (Xilinx Answer 56293).

Note: If Rev2 patch is installed, it is not necessary to install Rev1 patch first.

Supported Devices can be found in the following locations:


  • Open the Vivado tool -> IP Catalog, right-click on an IP and select Compatible Families.

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v4.0 (Rev.2) 2015.4
v4.0 (Rev.1) 2015.3
v4.0 2015.2
v3.3 2015.1
v3.2 (Rev.1) 2014.4
v3.2 2014.3
v3.1 (Rev.2) 2014.2
v3.1 (Rev.1) 2014.1
v3.1 2013.4
v3.0 2013.3
v2.0 2013.2
v2.0 2013.1
v1.6 2012.4

Changes in v3.3

  • Reduced transmit path latency by one clock in BUF layer(log_clk) and PHY layer(phy_clk) respectively
  • Fixed functional issues around error injection and packet cancellation
  • Updated GTH wrappers for current release
  • Added fairness algorithm as user choice in GUI
  • Transceiver control and status ports: added gt_txinhibit and gt_pcsrsvdin[]

Known and Resolved Issues

The following table provides known issues for the LogiCORE IP Serial RapidIO Gen2 core, starting with v2.0, initially released in Vivado Design Suite 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 63900) SRIO Gen2: Auto Upgrade from v3.2 to v3.3 in 2015.1 v3.3 v4.0
(Xilinx Answer 62375) LogiCORE IP Serial RapidIO Gen2 v3.2 - HELLO Format support in example design simulation v3.2 v3.3
(Xilinx Answer 64814) IP core Update for A7 GTP v3.2 v4.0 Rev1
(Xilinx Answer 64474) Soft_reset is connected to GND v3.2 v3.3
(Xilinx Answer 63362) 7 series GTH Wrapper Update v3.2 v3.3
(Xilinx Answer 57903) Incorrect ooc.xdc file generated with the core v3.0 v3.2
(Xilinx Answer 55826) Packets stalling in TX Buffer v2.0 v2.0 Rev1
(Xilinx Answer 55739) No packets transferred in example design simulation v2.0 v2.0 Rev1
(Xilinx Answer 55724) Data following truncated clock compensation sequence not descrambled correctly in IDLE2 v2.0 v2.0 Rev1
(Xilinx Answer 53937) phy_link_reset does not work
v1.6
v2.0
(Xilinx Answer 55340) Occasional PNAs seen for x1 configurations running with IDLE2 v1.6 v2.0
(Xilinx Answer 53542) Link might train down on 6.25Gbaud x2 and 6.25Gbaud x4 core configurations v1.6 v3.2
(Xilinx Answer 55341) The tool generates the same GT Wrapper XCO file for both Kintex-7, Virtex-7, and Zynq Devices v1.6 v3.0
(Xilinx Answer 54372) Support for devices with GTH v1.6 v3.3
(Xilinx Answer 55153) Core generated for Artix-7 production device fails in behavioral simulation with "ERROR: TEST FAILED" message v2.0 v2.0 Rev1


Other Information:

Revision History


04/03/2013 Initial release
04/29/2013 Added (Xilinx Answer 55724), (Xilinx Answer 55737), (Xilinx Answer 55826) and (Xilinx Answer 55739)
07/05/2013 Updated with link to Rev2 patch.
11/08/2013 Updated for 2013.3
11/18/2013 Added (Xilinx Answer 58402)
06/17/2015 Updated Version Table
06/17/2015 Updated Changes
06/17/2015 Added (Xilinx Answer 64074), (Xilinx Answer 63362), (Xilinx Answer 64474) and (Xilinx Answer 64814)
06/18/2015 Added (Xilinx Answer 62375) and (Xilinx Answer 63900)

Linked Answer Records

Child Answer Records

AR# 54648
Date Created 02/28/2013
Last Updated 03/02/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3
IP
  • Serial RapidIO