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AR# 54662

LogiCORE IP Block Memory Generator - Release Notes and Known Issues for Vivado 2013.1 and newer tools

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE Block Memory Generator; and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE Block Memory Generator IP Page:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
Version 8.3 (Rev. 4)2016.3
Version 8.3 (Rev. 3)2016.2
Version 8.3 (Rev. 2)2016.1
Version 8.3 (Rev. 1)2015.4.2
Version 8.3 (Rev. 1)2015.4.1
Version 8.3 (Rev. 1)2015.4
Version 8.32015.3
v8.2 Rev. 52015.2.1
v8.2 Rev. 52015.1
v8.2 Rev. 52015.1
v8.2 Rev. 42014.4.1
v8.2 Rev. 32014.4
v8.2 Rev. 22014.3
v8.2 Rev. 12014.2
v8.22014.1
v8.12013.4
v8.0 Rev. 22013.3
v8.0 Rev. 12013.2
v8.02013.1

General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP Block Memory Generator Core.

Answer RecordTitle
(Xilinx Answer 50918)LogiCORE IP LogiCORE Block Memory Generator - Release Notes and Known Issues


Change log History

2016.3:

  • Version 8.3 (Rev. 4)
  • Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
  • Other: Enable support for future devices
  • Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

2016.2:

  • Version 8.3 (Rev. 3)
  • Updated the IP to not set WRITE_DEPTH parameter to 8192 every time the mode is switched to BRAM_Controller
  • Updated the IP to support the device package changes
 
2016.1:

  • Version 8.3 (Rev. 2)
  • Updated the IP to deliver only Verilog behavioral model
  • Updated the IP to support UltraRAM in IP Integrator
  • Updated the IP to support the device package changes
 
2015.4.2:

  • Version 8.3 (Rev. 1)
  • No changes
 
2015.4.1:

  •  Version 8.3 (Rev. 1)
  •  No changes
 
2015.4:

  • Version 8.3 (Rev. 1)
  • Updated the IP to support the device package changes
 
2015.3:

  • Version 8.3
  • IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
  • New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
  • Simulation models are delivered in VHDL only
 
2015.2.1:

  • Version 8.2 (Rev. 5)
  • No changes
 
2015.2:

  • Version 8.2 (Rev. 5)
  • No changes


2015.1:
  • Version 8.2 (Rev. 5)
  • Delivering non encrypted behavioral models
  • Supported memory depth is increased up to 1M words
  • Added the power saving feature (RDADDRCHG) for UltraScale devices
  • Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
  • Version 8.2 (Rev. 4)
  • Updated the IP to support the device package changes

2014.4:
  • Version 8.2 (Rev. 3)
  • Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
  • Added support for 7 series Automotive (XA) and Defense Grade (XQ) devices
  • Internal device family change, no functional changes

2014.3:
  • Version 8.2 (Rev. 2)
  • Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
  • Fixed the GUI crash in Simple Dual Port RAM
  • Added support of all write modes in Simple Dual Port RAM when ECC is not used
  • Increased the supported depth to a maximum value of 256k

2014.2:
  • Version 8.2 (Rev. 1)
  • Updated the GUI tool tip for Byte write enable in page 1 of the block memory generator GUI

2014.1:

  • Version 8.2
  • Added support for the cascaded Primitives of widths 1 and 2 for UltraScale devices
  • Added support for the ECCPIPE register in the built-in ECC mode for UltraScale devices
  • Added support for dynamic power saving for UltraScale devices
  • Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7 series devices
  • Internal device family name change, no functional changes


2013.4:

  • Version 8.1
  • The Primitive output registers are made "ON" by default in the stand alone mode
  • Added cascaded support for UltraScale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
  • Added support for UltraScale devices


2013.3:

  • Version 8.0 (Rev. 2)
  • Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator.
  • Improved GUI speed and responsiveness, no functional changes
  • Reduced synthesis and simulation warnings
  • Added support for Cadence IES and Synopsys VCS simulators
  • Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
  • Changed BRAM Interface DIN and DOUT to match bus interface directions.


2013.2:

  • Version 8.0 (Rev. 1)
  • No Changes


2013.1:

  • Version 8.0
  • Native Vivado Release
  • There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.


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Revision History
04/03/2013 - Initial release
11/06/2013 - Updated for 2013.3

AR# 54662
Date Created 02/28/2013
Last Updated 10/13/2016
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
Tools
  • Vivado Design Suite
IP
  • Block Memory Generator