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AR# 54666 IP Release Notes and Known Issues for LogiCORE XAUI for Vivado 2013.1 and Forward

Description

This answer record contains the Release Notes and Known Issues for the XAUI Core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE XAUI Core IP Page:
http://www.xilinx.com/products/ipcenter/XAUI.htm

Solution


General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
Core Version Vivado Tools Version
v11.0 2013.1
v10.4 2012.2
v10.3 2012.1

General Guidance
The table below provides Answer Records for general guidance when using the LogiCORE XAUI core.
Article Number Article Title
(Xilinx Answer 38279) Ethernet IP Solution Center
(Xilinx Answer 33596) XAUI Frequently Asked Questions (FAQ)
(Xilinx Answer 55077)
 Ethernet IP Cores - Design Hierarchy in Vivado


Known and Resolved Issues
The following table provides known issues for the XAUI core, starting with v11.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Article Number Article Title Version Found Version Resolved
(Xilinx Answer 55132) Artix 7 - 20G DXAUI - Marginal timing seen v11.0 Workaround in AR
(Xilinx Answer 55226) Critical Warning - No cells match DRP path for false path constraint v11.0 Workaround in AR
(Xilinx Answer 55009) 7 Series GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode v10.4 v11.0
(Xilinx Answer 53779) Virtex-7 GTH Transceiver - RX Reset Sequence Requirement for Production Silicon v10.4 v11.0
(Xilinx Answer 53561) Artix-7 - RX Reset Sequence Requirement for Production Silicon  v10.4 v11.0
(Xilinx Answer 50848) 7 Series GT Transceivers - Reset maybe needed after disabling Loopback v10.3 v11.0
(Xilinx Answer 50795) 7 Series - Timing failures might occur in XAUI Example Design v10.4 v11.0


Revision History:
04/03/2013 - Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
55226 LogiCORE XAUI v11.0 - Vivado - Critical Warning - No cells match DRP path for false path constraint N/A N/A
55132 LogiCORE XAUI v11.0 - Vivado - Artix-7 - 20G DXAUI - Marginal timing seen N/A N/A
55077 Ethernet IP - Design hierarchy in Vivado tools N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
55009 Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode N/A N/A

Actions

AR# 54666
Date Created
Last Updated 04/01/2013
Status Active
Type Release Notes
IP
  • XAUI
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