This answer record contains the Release Notes and Known Issues for the 1G/2.5G Ethernet PCS/PMA or SGMII Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII Core IP Page:
Note: Prior to the 2015.1 release, the core was named Ethernet1000BASE-X PCS/PMA or SGMII as 2.5G support was not added.
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|v15.2 (Rev. 1)||2016.2|
|v15.1 (Rev. 1)||2015.4|
|v15.0 (Rev. 1)||2015.2|
|v14.3 (Rev. 1)||2014.4|
|v14.2 (Rev. 1)||2014.2|
The table below provides answer records for general guidance when using the LogiCORE IP1G/2.5G Ethernet PCS/PMA or SGMII core.
|(Xilinx Answer 38279)||Ethernet IP Solution Center|
|(Xilinx Answer 55077)||Ethernet IP Cores - Design Hierarchy in Vivado|
|(Xilinx Answer 64835)||Design Advisory for 1G/2.5G Ethernet PCS/PMA or SGMII v15.0 (Rev1) and earlier - Fabric Elastic Buffer overflow will cause RXBUFERR to toggle and Auto-Negotiation to restart and never complete|
Known and Resolved Issues
The following table provides known issues for the 1G/2.5G Ethernet PCS/PMA or SGMII core, starting with v12.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version |
|(Xilinx Answer 67883)||1G/2.5G Ethernet PCS/PMA or SGMII for UltraScale/UltraScale+ v15.2 (Rev1) and earlier -Fabric Elastic Buffer overflow will cause RXBUFERR to toggle and Auto-Negotiation to restart and never complete||v15.2(Rev.1)||2016.3|
|(Xilinx Answer 66031)||1G/2.5G Ethernet PCS/PMA or SGMII v15.1 (Rev.1) - Auto-Negotiation intermittently fails to complete with the core||v151 (Rev1)||2016.1|
|(Xilinx Answer 66030)||1G/2.5G Ethernet PCS/PMA or SGMII v15.1 - Auto-Negotiation intermittently fails to complete with the core||v15.1||2016.1|
|1G/2.5G Ethernet PCS/PMA or SGMII v15.0 (Rev1) or earlier - LVDS Transceiver - Soft reset can cause data corruption in LVDS Transceiver||v15.0 (Rev1)||2015.3|
|(Xilinx Answer 64224)||1G/2.5G Ethernet PCS/PMA or SGMII v15.0 - Timing failure on RST pin on IDELAYCTR||v15.0||2015.3|
|(Xilinx Answer 64143)||1G/2.G Ethernet PCS/PMA or SGMII v15.0 - Simulation errors are seen for UltraScale GTHE3 model||v15.0||See Answer Record|
|(Xilinx Answer 63844)||LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v14.3 or earlier - UltraScale SGMII over LVDS - The core does not recover from sporadic application of resets||v14.3 (Rev1)||v15.0|
|(Xilinx Answer 62072)||Ethernet 1000BASE-X PCS/PMA or SGMII - UltraScale - SGMII over LVDS Synchronization intermittently lost||v14.3 (Rev1)||v15.0|
|(Xilinx Answer 63441)||UltraScale GTH - free running clock update||v14.3||v15.0|
|(Xilinx Answer 62900)||UltraScale - 1000BASE-X over LVDS not supported||v14.3||See Answer-Record|
|(Xilinx Answer 62666)||7 Series - GTX/GTH - Intermittent link up failures seen||v14.3||v14.3 (Rev. 1)|
|(Xilinx Answer 62072)||UltraScale - SGMII over LVDS Synchronization intermittently lost||v14.2||NA|
|(Xilinx Answer 62377)||SGMII - 7 Series Transceiver interface with Fabric Elastic Buffer - Auto-Negotiation can fail to complete||v14.2||v14.3|
|(Xilinx Answer 62359)||7 Series - Link does not come back up after Cable pull/replug or link partner reset||v14.1||v14.3 (Rev. 1)|
|(Xilinx Answer 60784)||GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recover||v14.2||v14.2 (Rev. 1)|
|(Xilinx Answer 60204)||SGMII and 1588 - Updated XDC constraints needed to meet timing||v14.2||Work-around in answer record|
|(Xilinx Answer 60086)||Verilog - SGMII over LVDS - Synthesis Fails||v14.2||v14.2 (Rev. 1)|
|(Xilinx Answer 58020)||MMCM_LOCKED output needs to be connected to reset logic||v14.0||v14.1|
|(Xilinx Answer 55360)||mmcm_locked not connected to GT tx_startup_fsm and rx_startup_fsm ||v12.0 specific||Work-around in answer record|
|(Xilinx Answer 55367)||7 Series GTP and GTH - Update to RX termination||v12.0||v14.0|
|(Xilinx Answer 53779)||Virtex-7 GTH Transceiver - RX Reset Sequence Requirement for Production Silicon||v11.4||v12.0|
|(Xilinx Answer 53561)||Artix-7 - RX Reset Sequence Requirement for Production Silicon||v11.4||v12.0|
|N/A||Synchronization logic added to 7 Series GT tx_startup_fsm and rx_startup_fsm inputs||v11.4||v12.0|
|(Xilinx Answer 53444)||After disabling AN, AN sequences may still be transmitted if core has not gained Synchronization yet||v11.4|