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AR# 54668

LogiCORE IP QSGMII - Release Notes and Known Issues for Vivado 2013.1 and Forward

Description

This answer record contains the Release Notes and Known Issues for the QSGMII Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE QSGMII IP Page:

http://www.xilinx.com/content/xilinx/en/products/intellectual-property/qsgmii.html

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v3.3 (Rev. 6)2016.3
v3.3 (Rev. 5)2016.2
v3.3 (Rev. 4)2016.1
v3.3 (Rev. 3)2015.4
v3.3 (Rev. 2)2015.3
v3.3 (Rev. 1)2015.2
v3.32015.1
v3.2 (Rev. 3)2014.3
v3.2 (Rev. 2)2014.3
v3.2 (Rev. 1)2014.2
v3.22014.1
v3.12013.4
v3.02013.3
v2.0 (Rev. 1)2013.2
v2.02013.1
v1.42012.3
v1.32012.2
v1.22012.1


General Guidance

The table below provides answer records for general guidance when using the LogiCORE QSGMII core.

Answer RecordTitle
(Xilinx Answer 38279)Ethernet IP Solution Center
(Xilinx Answer 55077)Ethernet IP Cores - Design Hierarchy in Vivado

Known and Resolved Issues

The following table provides known issues for the ABC core, starting with v6.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 61134)QSGMII V3.2: Data mismatch or frame error seen with Example Test Bench Simulation when 3C Data is present in the Frame.v3.2See Answer Record
(Xilinx Answer 60784)GTP - Production reset DRP sequence could get in hung state that requires reconfiguration to recover v3.2v3.2 (Rev. 1)
(Xilinx Answer 60084)QSGMII v3.2 - UltraScale - PHY mode - Post Synthesis Simulation failures are seen v3.2Not Resolved
(Xilinx Answer 58108)Update to RX termination for 7 Series GTHv1.4v3.0
NAUpdates to 7 Series GTP/GTX/GTH Transceiver wrapper files for production support v1.4v2.0

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45711 LogiCORE IP QSGMII - Release Notes and Known Issues for 1.x N/A N/A
AR# 54668
Date Created 02/28/2013
Last Updated 10/13/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3
IP
  • QSGMII