^
Advanced Search

AR# 54673 MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled

Description

Version Found: MIG 7 Series 1.8
Version Resolved: See (Xilinx Answer 45195)

When generating a MIG 7 Series DDR3 design with Debug Signals enabled, a few of the Write Leveling Calibration debug signals are not connected properly to the Write ILA ChipScope core. The incorrect connections are on wl_po_coarse_cnt, wl_po_fine_cnt, rd_data_edge_detect_r, and wl_edge_detect_valid_r. This answer record shows how to manually correct these ILA connections until this issue is resolved in a future MIG 7 Series release.

Solution

The user_design/rtl/core_name.v module includes the connection of the debug signals to the ChipScope ILA cores.Open this module and locate the "ILA for monitoring write path signals" section. The required connection updates are shown below.The port numbers in comments are the old/incorrect connections.
//*******************************************************
// - ILA for monitoring write path signals,
// and synchronized read data
//*******************************************************
assign rd_data_edge_detect_r = dbg_phy_wrlvl[67+:9]; //66
assign wl_po_fine_cnt = dbg_phy_wrlvl[76+:54]; //75
assign wl_po_coarse_cnt = dbg_phy_wrlvl[130+:27]; //129
assign ddr3_ila_wrpath[10] = dbg_phy_wrlvl[60]; //59// wl_edge_detect_valid_r
assign ddr3_ila_wrpath[96+:54] = dbg_phy_wrlvl[76+:54]; //75
assign ddr3_ila_wrpath[150+:27]= dbg_phy_wrlvl[130+:27]; //129

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45195 MIG 7 Series - Release Notes and Known Issues for All Versions N/A N/A

Actions

AR# 54673
Date Created 03/01/2013
Last Updated 03/01/2013
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
Feed Back