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AR# 54688

LogiCORE IP AXI 1G/2.5G Ethernet Subsystem Core - Release Notes and Known Issues for Vivado 2013.1 and later tool versions

Description

This answer record contains the Release Notes and Known Issues for the AXI Ethernet Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and later tool versions.

LogiCORE AXI Ethernet Core IP Page:

http://www.xilinx.com/content/xilinx/en/products/intellectual-property/axi_ethernet.html

Note: Prior to the 2015.1 release, the AXI 1G/2.5G Ethernet Subsystem Core was called AXI Ethernet as we did not have 2.5G support.

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v4.02013.1
v5.02013.2
v6.02013.3
V6.0 (Rev .1)2013.4
v6.12014.1

v6.1 (Rev. 1)

2014.2
v6.22014.3
v6.2 (Rev. 1)2014.4
v7.02015.1
v7.0 (Rev. 1)2015.2
v7.0 (Rev. 2)2015.3
v7.0 (Rev. 3)2015.4
v7.0 (Rev. 4)2016.1
v7.0 (Rev. 5)2016.2


General Guidance

The table below provides answer records for general guidance when using the LogiCORE AXI Ethernet core.

Answer RecordTitle
(Xilinx Answer 55248)Vivado Timing and IP Constraints


Known and Resolved Issues

The following table provides known issues for the AXI 1G/2.5G Ethernet Subsystem core, starting with v4.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Please also refer to Tri-Mode Ethernet MAC (Xilinx Answer 54251) and 1G/2.5G Ethernet PCS/PMA or SGMII (Xilinx Answer 54667) IPs for a complete list of known issues.

Answer RecordTitleVersion
Found
Version
Resolved
(Xilinx Answer 65767)2015.3 AXI Ethernet designs with LwIP software are not working correctly in KCU105, VCU108 and VCU110 UltraScale boards7.0 (Rev. 2)See Answer Record
(Xilinx Answer 64241)AXI 1G/2.5G Ethernet Subsystem v7.0 - The core currently does not meet timing on 2.5G designs for -2L and -1LV devices v7.0See Answer Record
(Xilinx Answer 64833)2015.1 AXI Ethernet/RGMII - LWIP is not working on Artix devices. v7.0v7.0 (Rev1)
(Xilinx Answer 64223)Vivado IPI - AXI 1G/2.5G Ethernet Subsystem v6.2 or earlier - UltraScale SGMII over LVDS - idelay control element needs to be added manually for IPI design v6.2See Answer Record
(Xilinx Answer 64142)Vivado IPI - AXI 1G/2.5G Ethernet Subsystem v6.2 or earlier - UltraScale SGMII over LVDS - Synchronization and reset issue v6.2See Answer Record
(Xilinx Answer 63106)LogiCORE Tri-Mode Ethernet MAC, 10-Gigabit Ethernet MAC, AXI Ethernet and AXI 10G Ethernet- Vivado 2014.4 and earlier - AXI lite interface failures seen when using 64-bit masterv6.2See Answer Record
(Xilinx Answer 63914)AXI Ethernet v6.2 or earlier - UltraScale - SGMII over LVDS - Synchronization and reset issue v6.2See Answer Record
(Xilinx Answer 56024)AXI Ethernet v4.0 - SGMII interface is incorrectly configured for Auto-negotiationv4.0v5.0
(Xilinx Answer 58343)AXI Ethernet v6.0 system configured in FIFO mode fails peripheral tests owing to a Vivado tool issuev6.0v6.0
(Xilinx Answer 59504)Occasionally PHY_RESET_N is not de-asserted after powerupv2.01.av6.1

Linked Answer Records

Child Answer Records

AR# 54688
Date Created 03/01/2013
Last Updated 06/09/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
IP
  • AXI Ethernet