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AR# 54799

Vivado Synthesis - Warnings/Critical Warnings related to XDC constraints seen in Synthesis but not in Implementation.

Description

Warnings and Critical Warnings that objects in XDC constraints are not found are occasionally seen in Synthesis but not in Implementation.

Below are some examples:

WARNING: [Synth 8-3321] Empty from list for constraint at line 57 of xxxx.xdc.

CRITICAL WARNING: [Synth 8-3321] create_clock attempting to set clock on an unknown port/pin for constraint at line 41 of xxxx.xdc

WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-from [get_pins -hier -filter {NAME =~/RAM*/CLK}]'. ["xxxx.xdc":4]

WARNING: [Vivado 12-180] No cells matched ' <cell_name> '. ["xxxx.xdc":5]

WARNING: [Vivado 12-584] No ports matched ' <port_name> '. ["xxxx.xdc":36]

WARNING: [Vivado 12-508] No pins matched ' <pin_name> '. ["xxxx.xdc":35]

WARNING: [Vivado 12-507] No nets matched ' <net_name> '. ["xxxx.xdc":23]

WARNING: [Vivado 12-627] No clocks matched ' <clock_name> '. ["xxxx.xdc":24]

Why are these messages only seen in Synthesis?

Can these be safely ignored?

Solution

Below are some possible reasons why Synthesis will give an error that a constraint object (cell/net/pin) is not found but Implementation will not.

  1. The object is in an instantiated netlist (NGC/EDIF), DCP or OOC module.
    Synthesis treats these as a black box so it does not see the object.

  2. The corresponding object exists in the RTL netlist (Elaborated design) but with a different name.
    Object names can be changed during Synthesis.
    So the same object might have different names in the RTL netlist and the Synthesized netlist.


If the constraint is not important to Synthesis, the message can be safely ignored as the constraint works well post-Synthesis.

However, if you want to remove these messages, you can use the following solutions.

  1. Use "get_cells/get_pins" instead of "get_nets".
    The net name is more likely to be changed than the cell and pin name.
     
  2. Use "get_nets -of [get_pins xxx]" instead of querying the net name.

  3. Add "dont_touch" or "keep" attributes to the object in the RTL netlist (Elaborated design) to preserve the object name.

  4. If you cannot find a way to query the objects that works for both Synthesis and Implementation, put these constraints in a separate XDC file and set the "used_in" property of this XDC to "Implementation" only.
    If you want the constraints to work for Synthesis as well, revise the constraints according to the object names in the RTL netlist (Elaborated design), put the constraints in another separate XDC and set the "used_in" property to "Synthesis" only.
AR# 54799
Date Created 03/07/2013
Last Updated 04/18/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite