UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54878

LogiCORE IP AXI Video Direct Memory Access - Throughput/Bandwidth Limitations

Description

I am running into throughput and throttling issues from the AXI VDMA itself (i.e., the interconnect is sitting idle waiting for transactions, but I am getting throttled on the stream side of the AXI VDMA).

What is wrong?

Solution

There is a known limitation with the core (it is actually a limitation of the AXI Datamover upon which the AXI VDMA is built) where throughput suffers greatly if your stream-side clocks are faster than your memory map-side clocks.

Please ensure that your memory map clocks (excluding the AXI Lite clock) are at least as fast as your stream clocks.

Linked Answer Records

Master Answer Records

AR# 54878
Date Created 03/12/2013
Last Updated 04/04/2013
Status Active
Type General Article
IP
  • Video DMA
  • AXI Video Direct Memory Access
  • AXI Video DMA