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AR# 54879

2012.4 Vivado - Keep signals on edif netlist interpreted as mark_debug

Description

If I bring in an .edf into the Vivado tool with "keep" attributes on nets, when the synthesized design is opened by Vivado, those nets have mark_debug and save attributes added to them instead of keep attributes.

Solution

When keep attributes on signals in HDL are synthesized by Vivado Synthesis, the keep attributes are propagated to instances connected to these signals and taken off the signal itself in the .edf (in 2013.1, the keep attribute on the signal itself is changed to an rtl_keep attribute). XST and Synplify, however, might still have flows that put keep attributes on the nets themselves in the .edf, and these attributes will then be interpreted as mark_debug attributes in Vivado.

The work-around is to change the keep attributes to save attributes in the HDL.

AR# 54879
Date Created 03/12/2013
Last Updated 07/19/2013
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite