In the Vivado 2013.1 tool, if you upgrade from a previous version of the XADC Wizard IP with a Verilog instantiation, an error similar to the following occurs for each port:
"[Synth 8-448] named port connection 'DADDR_IN' does not exist for instance 'XADC_WIZ' of module 'xadc_wiz_v2_4_0' ["/design.srcs/sources_1/new/top.v":40]"
To drive consistency between Xilinx IPs, signal names in the Verilog version of the cores have been changed to use all lowercase, therefore, the signal names in the IP instantiation are now in lowercase.
In the example of the error message above, the DADDR_IN signal is now daddr_in in v3.0.
After the upgrade is completed, the instantiation in the design will need to be replaced with signal names in lowercase.