UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54997

XADC Wizard v3.0 - Verilog instantiation changed from uppercase to lowercase

Description

In the Vivado 2013.1 tool, if you upgrade from a previous version of the XADC Wizard IP with a Verilog instantiation, an error similar to the following occurs for each port:

"[Synth 8-448] named port connection 'DADDR_IN' does not exist for instance 'XADC_WIZ' of module 'xadc_wiz_v2_4_0' ["/design.srcs/sources_1/new/top.v":40]"

Solution

To drive consistency between Xilinx IPs, signal names in the Verilog version of the cores have been changed to use all lowercase, therefore, the signal names in the IP instantiation are now in lowercase.

In the example of the error message above, the DADDR_IN signal is now daddr_in in v3.0.

After the upgrade is completed, the instantiation in the design will need to be replaced with signal names in lowercase.

AR# 54997
Date Created 03/20/2013
Last Updated 03/28/2013
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
Tools
  • Vivado Design Suite - 2013.1
IP
  • XADC Wizard