When the TX buffer is bypassed, the TX phase alignment is used to adjust the phase difference between the PMA parallel clock domain (XCLK) and the TXUSRCLK domain. This can be performed automatically or manually controlled by the user. The TX buffer bypass is called a "multi-lane" mode when the TXOUTCLK is used as the source of the TXUSRCLK and shared among many lanes. In the GTX transceiver, the multi-lane buffer bypass mode is manual; in the GTH or GTP transceivers, multi-lane buffer bypass can be either manual or auto mode.
When bypassing the TX buffer, due to a corner case scenario, the internal TX synchronization/phase alignment state machine can hang waiting for a rising edge on TXPHINITDONE; refer to the "TX Phase and Delay Alignment in Manual Mode" Figure 3-24 in 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) or Figure 3-16 in 7 Series FPGAs GTP Transceivers User Guide (UG482). This behavior can be detected by observing the following ports on the transceiver and following the sequence of events as documented in these figures in the user guide.
- TXDLYRESET
- TXDLYRESETDONE
- TXPHINIT
- TXPHINITDONE
There are two types of behavior that can happen depending on the 7 series transceiver type:
Behavior #1
The TX Phase and Delay Alignment sequence gets stuck waiting for the rising edge on TXPHINITDONE because that signal might pulse low too quickly. Because TXPHINITDONE stays high only after the first phase alignment procedure, and might face this short low pulse issue on subsequent phase alignments, this can only occur during the second or subsequent phase alignments.
Behavior #2
The TX Phase and Delay Alignment sequence hangs because the TXPHINITDONE handshake can take too long and the TX sync state machine might time out. This is more likely to occur as the line rate decreases.
Solutions
GTX Transceiver:
Only behavior #1 pertains to the GTX transceiver.
When the customer design falls under any of the following categories, no change will be necessary to address behavior #1. However, keep in mind that for categories 1 and 2, the additional GTTXRESET might cause the TXOUTCLK to glitch and the user system must be immune to this glitch.
1. If GTXTXRESET is asserted before each phase alignment procedure.
2. When the user asserts GTTXRESET if phase alignment does not complete properly.
3. When the TX sync/phase alignment state machine is already in the fabric and clocked by the TXUSRCLK. An example is the PCIe IP from Xilinx.
For customer designs not falling under these categories, the user must update to the latest IP's in Vivado 2013.1 or 7 Series FPGAs Transceivers Wizard v2.5 in ISE 14.5/Vivado 2013.1.
GTH/GTP Transceivers:
Both behaviors #1 and #2 pertain to the GTH and GTP Transceivers. The user must update to the latest IP's in Vivado 2013.1 or 7 Series FPGAs Transceivers Wizard v2.5 in ISE 14.5/Vivado 2013.1 except when in the following use mode:
The TX buffer bypass section in the 7 Series FPGA GTX/GTH or GTP Transceivers User Guide will be updated with the correct use modes to reflect the information above. For the GTX/GTH user guide (UG476), this is expected to be in the next version, v1.9. For the GTP user guide (UG482), this is expected to be in the next version, v1.5.
Protocol Solutions
These solutions pertain only to the Xilinx IP that utilize or require the TX buffer bypass feature and are broken out by protocol.
XAUI/RXAUI:
The GTH and GTP buffer bypass use mode is changed from automatic to manual and the XAUI/RXAUI IP cores must be updated to the latest version in Vivado 2013.1. For GTX, manual mode is already being used.
CPRI:
The GTX, GTH and GTP buffer bypass use mode is changed from automatic to manual. The CPRI IP core must be updated to the latest version in Vivado 2013.1.
Revision History
04/05/2013 - Added ISE information and the exception case for GTH/GTP transceivers
04/03/2013 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 54473 | IP Release Notes and Known Issues for LogiCORE IP CPRI core for Vivado 2013.1 and and newer tool versions | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 54666 | IP Release Notes and Known Issues for LogiCORE XAUI for Vivado 2013.1 and Forward | N/A | N/A |
| 54249 | IP Release Notes and Known Issues for LogiCORE RXAUI for Vivado 2013.1 and Forward | N/A | N/A |
| 42944 | Design Advisory Master Answer Record for Virtex-7 FPGA | N/A | N/A |
| 42946 | Design Advisory Master Answer Record for Kintex-7 FPGA | N/A | N/A |
| 51456 | Design Advisory Master Answer Record for Artix-7 FPGA | N/A | N/A |