If the TX buffer is bypassed, the TX phase alignment is used to adjust the phase difference between the PMA parallel clock domain (XCLK) and the TXUSRCLK domain. This can be performed automatically, or manually controlled by the user. The TX buffer bypass is called a "multi-lane" mode when the TXOUTCLK is used as the source of the TXUSRCLK and shared among many lanes. In the GTX transceiver, the multi-lane buffer bypass mode is manual; in the GTH or GTP transceivers, multi-lane buffer bypass can be either manual or auto mode.
If bypassing the TX buffer, due to a corner case scenario, the internal TX synchronization/phase alignment state machine can hang waiting for a rising edge on TXPHINITDONE; refer to the "TX Phase and Delay Alignment in Manual Mode" Figure 3-24 in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) or Figure 3-16 in the 7 Series FPGAs GTP Transceivers User Guide (UG482). This applies to all silicon versions (Initial ES, General ES and Production) of the 7 Series FPGA GTX/GTH/GTP Transceivers.
This behavior can be detected by observing the following ports on the transceiver and following the sequence of events as documented in the figures in the user guide.
There are three types of behavior that can occur depending on the 7 series transceiver type:
The TX Phase and Delay Alignment sequence gets stuck waiting for the rising edge on TXPHINITDONE because that signal might pulse Low too quickly. Because TXPHINITDONE stays High only after the first phase alignment procedure, and might face this short low pulse issue on subsequent phase alignments, this can only occur during the second or subsequent phase alignments.
The TX Phase and Delay Alignment sequence hangs because the TXPHINITDONE handshake can take too long and the TX sync state machine might timeout. This is more likely to occur as the line rate decreases.
Phase Initialize Timeout Update
The TX Phase and Delay Alignment sequence can fail because the example design timeout in 7 Series FPGAs Transceivers Wizard v2.6 in ISE 14.6/Vivado 2013.2 or earlier for phase initialization is too short in some situations.
Phase Initialize Timeout Update GTX, GTH, and GTP
The phase initialization process can fail because the timeout for phase initialization is too short in some situations. The formula for determining what the timeout should be is:
1024*pll output divider*internal data path width + 1024+640+3200
where internal data path width is equal to 16,20,32 or 40 and pll output divider is equal to the TXOUT_DIV attribute unless the design uses rate changes in which case it will be equal to the divider set by TXRATE (see table 3-25 of UG476 or table 3-23 of UG482).
For example designs, the file *tx_startup_fsm.v contains on or near line 165:
parameter MAX_WAIT_BYPASS = 110000;
The MAX_WAIT_BYPASS number needs to be updated with the value from the equation above. For multilane designs, the result will need to be multiplied by 2 since the master lane has to align, and then the slave lanes align in parallel.
Any change to the timeout calculated here must be applied to 7 Series FPGAs Transceivers Wizard v2.6 in ISE 14.6/Vivado 2013.2 or earlier. It is an addition to the changes below.
In addition to the timeout update, only behavior #1 pertains to the GTX transceiver.
When the customer design follows any of the following, no change will be necessary to address behavior #1.
If none of the above three apply, you must update to the latest IPs in the Vivado 2013.1 tool, or 7 Series FPGAs Transceivers Wizard v2.5 in ISE 14.5/Vivado 2013.1 design tools (and update the phase initialization timeout if necessary).
Note: When asserting an additional GTTXRESET as per 1 or 2 above, the TXOUTCLK may glitch and will be unreliable until the user completes the reset sequence (TXRESETDONE) and the phase alignment process is complete.
In addition to the timeout update, both behaviors #1 and #2 pertain to the GTH and GTP Transceivers. You must update to the latest IPs in Vivado 2013.1 tool, or 7 Series FPGAs Transceivers Wizard v2.5 in ISE 14.5/Vivado 2013.1 design tools (and update the phase initialization timeout if necessary), except when in the following use mode:
The TX buffer bypass section in the 7 Series FPGA GTX/GTH Transceivers User Guide is updated with the correct use modes to reflect the information above in v1.9 of UG476. For the GTP user guide (UG482).
For Behavior #3 the timeout for the phase initialization process is in the example design file
These solutions pertain only to the Xilinx IP that utilize or require the TX buffer bypass feature and are broken out by protocol.
The GTH and GTP buffer bypass use mode is changed from automatic to manual and the XAUI/RXAUI IP cores must be updated to the latest version in the Vivado 2013.1 tool. For GTX, manual mode is already being used.
The GTH and GTP buffer bypass use mode is changed from automatic to manual. The CPRI IP core must be updated to the latest version in the Vivado 2013.1 tool.
09/24/2013 - Clarified the TXPHINITDONE timeout equation
08/05/2013 - Added information on fixing the phase initialization timeout
05/13/2013 - Added ISE design tool answer record links for the IPs; corrected the typo GTXTXRESET to GTTXRESET
04/12/2013 - Minor updates to the GTX and GTH/GTP transceivers section
04/05/2013 - Added ISE information and the exception case for GTH/GTP transceivers
04/03/2013 - Initial release