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AR# 55039 MIG 7 Series DDR3/DDR2 - Changing the Traffic Generator Address Pattern to PRBS results in SEQUENTIAL addressing.

Description

Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)

The Traffic Generator provided with the MIG 7 Series DDR3/DDR2 Example Design includes the ability to change the address pattern within ChipScope VIO by changing "vio_addr_mode_value".  When changing this to send a PRBS address pattern, a sequential address sequence is seen.

Solution

This is a known issue and will be resolved in a later version of MIG 7 Series.

In the meantime, the remaining address patterns can be used for hardware analysis.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45195 MIG 7 Series - Release Notes and Known Issues for All Versions N/A N/A

Actions

AR# 55039
Date Created 03/27/2013
Last Updated 03/27/2013
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
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