We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55056

MIG 7 Series DDR2/DDR3 - AXI Interface Enabled - During continuous read or write commands, bubbles/gaps are seen between the user interface bursts


Version Found: MIG 7 Series v1.8
Version Resolved: See (Xilinx Answer 45195)

When the MIG 7 Series DDR3/DDR2 controller with the AXI interface enabled receives continuous read or write commands, there will be bubbles/gaps between the user interface app signals. 

This results in a loss of efficiency.


This behavior is caused by the AXI write and read state machine.

The state machine cannot continuously send out UI commands.

When the AXI burst is short, it will result in the greatest performance loss.

The current workaround is to use long AXI bursts, which will reduce the bubbles/gaps but will not remove them completely.

This issue is fixed in the 2013.2 release.
AR# 55056
Date Created 03/22/2013
Last Updated 08/13/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series