Version Found: MIG 7 Series v1.8
Version Resolved: See (Xilinx Answer 54025)
This answer record applies to MIG 7 Series DDR3/DDR2 designs with the AXI interface enabled.
When a long write or read burst is requested on the AXI interface and AXI is currently servicing a read request, there is chance that AXI will service the write request before the read request is completed.
After all write requests are served, AXI will send out the remaining read requests.
This is an AXI arbiter problem. The logic should not switch to write before read is completed.
This generally does not impact the functionality, but for designs that require strict write and read order, this can cause a functional problem.
The work-around for this issue is to not assert write and read at the same time. After the read is completed, the write should be then requested on AXI.
There is no starvation timeout or wait timeout.
This issue is fixed in Vivado 2013.2 and later.
03/06/2017 - Added Version Found and Version Resolved